Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-06-06
2001-09-11
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S205000, C365S190000, C365S203000
Reexamination Certificate
active
06288928
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having memory cells, and more particularly to a technology for performing write operations at high speed.
2. Description of the Related Art
FIG. 1
shows the configuration of the main parts in a semiconductor integrated circuit of this type. In the drawings, those signal lines shown by thick lines are composed of a plurality of lines each. Some of the blocks connected with the thick lines are composed of a plurality of circuits.
The semiconductor integrated circuit comprises an input/output control unit
1
, a core control unit
2
, and a memory core
3
.
The input/output control unit
1
comprises a clock buffer
4
, a command buffer
5
, a row address buffer
6
, a column address buffer
7
, an input/output buffer
8
, and a command decoder
9
.
The clock buffer
4
receives a clock signal CLK, and outputs an internal clock signal ICLK. The command buffer
5
accepts a command signal CMD in synchronization with the internal clock signal ICLK, and outputs the accepted signal as an internal command signal ICMD.
The row address buffer
6
accepts a row address signal RAD in synchronization with the internal clock signal ICLK, and outputs the accepted signal as an internal row address signal IRAD. The column address buffer
7
accepts a column address signal CAD in synchronization with the internal clock signal ICLK, and outputs the accepted signal as an internal column address signal ICAD.
The input/output buffer
8
, in a write operation, accepts a data signal DQ in synchronization with the internal clock signal ICLK, and outputs the same in the form of an internal data signal IDQ. In a read operation, the input/output buffer
8
accepts an internal data signal IDQ in synchronization with the internal clock signal ICLK, and outputs the accepted signal as a data signal DQ.
The command decoder
9
receives the internal clock signal ICLK and the internal command signal ICMD, decodes the command, and generates control signals RDZ, WRZ, and the like for controlling the main circuits of the semiconductor integrated circuit. Here, the control signal RDZ is generated when a command signal CMD corresponding to a read operation is supplied. The control signal WRZ is generated when a command signal CMD corresponding to a write operation is supplied.
The core control unit
2
comprises an RAS generator
10
, a precharge generator
11
, a control circuit
12
, a predecoder
13
, a block decoder
14
, a CAS generator
15
, a control circuit
16
, a predecoder
17
, a word decoder
18
, a BRSZ generator
19
, a sense amplifier generator
20
, a column decoder
21
, a read control circuit
22
, a write control circuit
23
, a read buffer
24
, and a write buffer
25
. Of the circuits mentioned above, the RAS generator
10
, control circuit
12
, word decoder
18
, BRSZ generator
19
, sense amplifier generator
20
, and column decoder
21
function as a timing control unit
26
.
The RAS generator
10
receives the control signals RDZ and WRZ, and the precharging signal PREZ from the precharge generator
11
, and outputs a row controlling signal RASZ. The precharge generator
11
receives the row controlling signal RASZ, and outputs the precharging signal PREZ after a predetermined time.
The control circuit
12
receives the row controlling signal RASZ, generates a plurality of control signals RCON, and outputs the respective control signals RCON to the word decoder
18
, the BRSZ generator
19
, and the sense amplifier generator
20
.
The predecoder
13
receives the internal row address signal IRAD, and outputs a predecode signal RPDEC. The block decoder
14
receives part of the predecode signal RPDEC, generates a decode signal, and outputs this decode signal to the word decoder
18
, the BRSZ generator
19
, and the sense amplifier generator
20
.
The CAS generator
15
receives the control signals RDZ and WRZ, and outputs a column controlling signal CASZ. The control circuit
16
receives the column controlling signal CASZ, generates a plurality of control signals CCON, and outputs the respective control signals CCON to the column decoder
21
, the read control circuit
22
, and the write control circuit
23
.
The predecoder
17
receives the internal column address signal ICAD, and outputs a predecode signal CPDEC.
The read control circuit
22
receives the predecode signal CPDEC and the control signal CCON, and outputs a read data controlling signal RD. The write control circuit
23
receives the predecode signal CPDEC and the control signal CCON, and outputs a write data controlling signal WD.
The read buffer
24
receives the common date signals DBZ and DBX from the memory core
3
in synchronization with the read data controlling signal RD, and outputs the same in the form of the internal data signal IDQ. The write buffer
25
receives the internal data signal IDQ in synchronization with the write data controlling signal WD, and outputs the same to the memory core
3
in the form of the common data signals DBZ and DBX. Here, the common data signals DBZ and DBX are complementary signals.
The word decoder
18
receives a predetermined control signal RCON, the predecode signals RPDEC and CPDEC, and the decode signal from the block decoder
14
, generates a word line signal WLZ, and outputs the generated signal to the memory core
3
.
The BRSZ generator
19
receives a predetermined control signal RCON, the predecode signals RPDEC and CPDEC, and the decode signal from the block decoder
14
, generates a bit line controlling signal BRSZ, and outputs the generated signal to the memory core
3
.
The sense amplifier generator
20
receives a predetermined control signal RCON, the predecode signals RPDEC and CPDEC, and the decode signal from the block decoder
14
, generates a sense amplifier activating signal LEZ, and outputs the generated signal to the memory core
3
.
The column decoder
21
receives the control signal CCON and the predecode signal CPDEC, generates a column selecting signal CLZ, and outputs the generated signal to the memory core
3
.
The memory core
3
comprises a plurality of memory cells MC which are connected to word lines WL and bit lines BL (/BL) arranged vertically and horizontally. This example uses a DRAM memory core
3
.
FIG. 2
shows the main parts of the memory core
3
.
The memory core
3
comprises column switches
3
a
and
3
b
consisting of an nMOS, a sense amplifier
27
, an nMOS
3
c
for equalization, nMOSs
3
d
and
3
e
for precharge, and a memory cell MS, which are connected to complementary bit lines BL and /BL.
Either the sources or the drains of the column switches
3
a
and
3
b
are connected to the bit lines BL and /BL, respectively. The others are connected to the common data signals DBZ and DBX, respectively. The gates of the column switches
3
a
and
3
b
receive the column selecting signal CLZ.
The sense amplifier
27
comprises: a CMOS inverter consisting of a pMOS
27
a
and an nMOS
27
b
; a CMOS inverter consisting of a PMOS
27
c
and an nMOS
27
d
; and a pMOS
27
e
and nMOS
27
f
for supplying a driving voltage to the sources of the respective CMOS inverters. The inputs and outputs of the CMOS inverters are connected with each other, and the outputs are connected to the bit lines BL and /BL separately. The pMOS
27
e
has the drain connected to the sources of the pMOS
27
a
and pMOS
27
c
, and the source connected to a power supply line VDD. The gate of the PMOS
27
e
is supplied with the sense amplifier activating signal LEZ through an inverter
27
g
. The nMOS
27
f
has its drain connected to the nMOS
27
b
and nMOS
27
d
, and the source connected to a ground line VSS. The gate of the nMOS
27
f
is supplied with the sense amplifier activating signal LEZ.
The source and the drain of the nMOS
3
c
are connected to the bit lines BL and /BL, respectively. Either the sources or the drains of the nMOSs
3
d
and
3
e
are connected to the bit lines BL and /BL, respectively. The others are connected to a
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Lam David
Nelms David
LandOfFree
Semiconductor integrated circuit and method of controlling... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit and method of controlling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit and method of controlling... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2546114