Semiconductor integrated circuit and method for testing the...

Details Semiconductor integrated circuit and method for testing the... Semiconductor integrated circuit and method for testing the...

2004-07-29

2008-03-25

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Receivers

Interference or noise reduction

C375S373000, C375S375000, C375S376000, C375S316000, C375S224000, C714S703000, C714S706000, C714S704000, C714S715000, C714S814000

Reexamination Certificate

active

07349506

ABSTRACT:
A method and semiconductor integrated circuit in which a receiver receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter which receives parallel transmission data and executes serial transmission processing on the basis of the clock signal, and having a loop back function of supplying data output from the transmitter to the receiver for test. The receiver capable of executing control so as to make a phase of the input data coincide with that of a recovery clock.

REFERENCES:
patent: 5787114 (1998-07-01), Ramamurthy et al.
patent: 5859881 (1999-01-01), Ferraiolo et al.
patent: 6076175 (2000-06-01), Drost et al.
patent: 6861868 (2005-03-01), Agrawal et al.
patent: 7218670 (2007-05-01), Lesea et al.
patent: 2004/0247022 (2004-12-01), Raghavan et al.
patent: 2005/0135501 (2005-06-01), Chang et al.

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