Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-12-05
2003-10-21
Hirshfeld, Andrew H. (Department: 2854)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S719000, C324S763010, C324S1540PB, C324S761010
Reexamination Certificate
active
06636066
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a semiconductor integrated circuit provided with a plurality of output buffers and a method for testing the same, and more particularly to a semiconductor integrated circuit, which can realize the measurement of a resistance value of output buffers with high accuracy and a method for testing the same.
BACKGROUND OF THE INVENTION
In performing a test on electric characteristics of a semiconductor integrated circuit, it is common practice to connect an IC (integrated circuit) tester to the semiconductor integrated circuit through a test substrate. This method is disadvantageous in that, when the resistance value of output buffers of the semiconductor integrated circuit as the test object is measured, a measurement error occurs due to contact resistance caused by the connection of the IC tester to the test substrate.
Accordingly, a conventional testing method proposed for reducing the measurement error derived from the contact resistance will be explained. This testing method is disclosed, for example, in Japanese Patent No. 2765508.
FIG. 1
is a block diagram showing the structure of an output buffer and an IC tester provided in a conventional semiconductor integrated circuit.
When the output buffer provided in the semiconductor integrated circuit is a high-drive output buffer, the output buffer B
101
comprises low-drive output buffers B
102
-
1
to B
102
-N, which are connected parallel to each other, between an input terminal IN
101
and an output terminal P
101
. Control signals en
1
to enN are supplied respectively to the output buffers
102
-
1
to
102
-N.
On the other hand, in the IC tester TEST
2
, an ammeter
1
and a voltmeter
2
, which have been connected in series to each other, are provided between an input terminal and a ground.
In the conventional semiconductor integrated circuit having the above construction, at the time of usual operation, all the control signals en
1
to enN are made valid to operate all the low-drive output buffers B
102
-
1
to B
102
-N. This permits the signal input into the input terminal IN
101
to be output by high-capability drive from the output terminal P
101
.
On the other hand, in measuring the resistance value of the high-drive output buffer B
101
with the IC tester TEST
2
, only a control signal eni, wherein i represents a natural number of 1 to not more than N, corresponding to the ith output buffer B
102
-i among the N low-drive output buffers, B
102
-
1
to B
102
-N, is made valid while control signals enj (j≠i) corresponding to the other low-drive output buffers are made invalid. As a result, the input signal is driven by the output buffer B
102
-i. On the other hand, the output of the other output buffers is brought to a high-impedance state (Hi-z), and the logical level of the output terminal P
101
is brought to a high level or a low level. In this state, the resistance value of the low-drive output buffer B
102
-i can be measured with the IC tester TEST
2
. For all the low-drive output buffers B
102
-
1
to B
102
-N, this operation may be successively carried out while varying the i value to measure the resistance value of the high-drive output buffer B
101
.
According to this testing method, when the high-drive output buffer is realized by a single high-drive output buffer, the resistance value at the time of the measurement is R+R
0
wherein R
0
represents the resistance value of a contact resistor C
101
caused by the connection of the IC tester TEST
2
to the test substrate and R represents the resistance value of the high-drive output buffer B
101
, whereas, when the high-drive output buffer B
101
is constituted by N low-drive output buffers, the resistance value at the time of measurement is N×R+R
0
. Therefore, when the high-drive output buffer B
101
is constituted by N low-drive output buffers, the measurement error caused by the contact resistance between the IC tester TEST
2
and the test substrate can be lowered.
In this conventional testing method, however, although the measurement error caused by the contact resistance between the IC tester TEST
2
and the test substrate can be lowered, the measurement error caused by the contact resistance cannot be fully eliminated.
Semiconductor integrated circuits have recently become used in various applications, and this has led to various demands for electrical characteristics of semiconductor integrated circuits. For example, one of these demands is that a plurality of output terminals are provided and, regarding electrical characteristics of each output terminal, the resistance value for the output buffers connected respectively to the output terminal should be constant. When a test is performed with an IC tester on whether or not the resistance value of the plurality of high-drive output buffers is constant, the contact resistance caused by the connection of the semiconductor integrated circuit to the IC tester through a test substrate exists between each high-drive output buffer and the IC tester. For this reason, unless the contact resistance between each high-drive output buffer and the IC tester is constant, a measurement error attributable to a variation in contact resistance occurs. In the above conventional testing method, however, the measurement error caused by the contact resistance cannot be fully eliminated, although a reduction in the measurement error is possible. Therefore, when a variation in contact resistance has occurred, disadvantageously, the test on whether or not the resistance value of the plurality of high-drive output buffers is constant cannot be accurately performed.
Accordingly, in order to measure the resistance value of input/output buffers while eliminating the influence of the contact resistance, a method for testing semiconductor circuits is disclosed, for example, in Japanese Patent Application Laid-Open No. 11-30649 (that corresponds to U.S. Pat. No. 6,150,831). In this publication, a circuit comprising a plurality of high-speed, small-amplitude input/output buffers connected to a control circuit is shown. Each high-speed, small-amplitude input/output buffer is provided with two transistors as two semiconductor switches which have been connected in series to each other. This publication describes that these two transistors are simultaneously brought to ON state to allow a breakthrough current to flow into these transistors, whereby the resistance value can be measured.
In Japanese Patent Application Laid-Open No. 11-30649, a timing chart showing the operation of the circuit shown in the drawing is described. From the timing chart and the description of the specification, however, it is not clear that, among the signals input into the high-speed, small-amplitude input/output buffers, which signal is a signal to be driven and which signal is a signal for controlling the operation of the high-speed, small-amplitude input/output buffer. Therefore, all of predetermined resistance values cannot be actually measured. Further, the voltage applied to the gate of each transistor is often brought to an unnecessarily large value. In this case, the semiconductor circuit is deteriorated in a short period.
SUMMARY OF THE INVENTION
In view of the above problems of the prior art, the invention has been made, and it is an object of the invention to provide a semiconductor integrated circuit and a method for testing the same, which can realize the measurement of the resistance value of high-drive output buffers with high accuracy without undergoing the influence of contact resistance caused between the semiconductor integrated circuit and an IC tester, and preferably can suppress the deterioration of the circuit.
According to the first feature of the invention, a semiconductor integrated circuit comprises:
a plurality of output buffers each comprising a P-channel transistor and an N-channel transistor, the P-channel transistor in its drain and the N-channel transistor in its drain having been commonly bonded to an external output terminal; and
a control circuit which, in measu
Hamdan Wasseem H.
Hirshfeld Andrew H.
NEC Electronics Corporation
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