Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2001-01-31
2002-08-20
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S189070, C365S230060
Reexamination Certificate
active
06438013
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit that is able to adjust the characteristics of internal circuits by a ROM circuit formed of a fuse and such.
2. Description of the Related Art
Recently, a semiconductor integrated circuit such as DRAMs has been operating at a high speed at a low voltage. In line therewith, it has become necessary that the voltage of the major nodes of internal circuits in this type of a semiconductor integrated circuit and timing of signals transmitted to these nodes are designed at the unit of, for example, 0.01V and 0.1 ns. However, the characteristics of elements such as transistors, resistors, capacitors, that constitute the semiconductor integrated circuit varies, depending on manufacturing lots, wafer positions in the manufacturing lots, or chip positions on the wafer. Therefore, it becomes difficult to design chips as in the minute design as described above.
In the prior arts, a technology has been developed, which produces semiconductor integrated circuits having the required characteristics by adjusting, through trimming, the characteristics that varies depending on such a manufacturing process. Herein, the trimming means changes in the connection of circuits and adjusting the characteristics of the circuits.
FIG. 1
shows a DRAM having this type of a trimming feature.
The DRAM has a plurality of pads
1
that receive signals from the exterior, an input buffer
2
, an address buffer
3
, a command decoder
4
, a test mode control circuit
5
, and a plurality of adjustment circuits
6
. The adjustment circuits
6
are, respectively, composed of an adjustment decoder
7
, a fuse circuit
8
and a selecting circuit
9
.
The input buffer
2
receives a clock signal CLK, a clock ENABLE signal CKE, and a command signal (/CS, /RAS, /CAS, or /WE) through the pads
1
, and outputs the received signal to the command decoder
4
. The address buffer
3
receives address signals A
0
through A
12
through the pads
1
, and outputs the received signals to the adjustment circuit
6
, address decoder (not shown) and such. The command decoder
4
decodes the received commands signals and outputs a control signal used in a normal operation mode, an entry signal ENTRY used in a testing mode and an exit signal EXIT as command signals.
The test mode control circuit
5
receives the entry signal ENTRY and exit signal EXIT, and outputs a latch signal LTCH and a reset RST, which actuate the adjustment circuit
6
in synchronization with these signals.
The adjustment decoders
7
of the respective adjustment circuits
6
receive address signals A
0
through A
12
, a latch signal LTCH and a reset signal RST, and outputs a test activating signal TACT. The test activating signal TACT is activated when receiving predetermined address signals A
0
through A
12
in synchronization with the latch signal LTCH, and is inactivated when receiving the reset signal RST.
The fuse circuit
8
has a fuse formed of polysilicon and such, and a control circuit. The fuse circuit
8
activates a fuse activating signal FACT when the fuse blows (when programming).
The selecting circuit
9
outputs an OR logic of the test activating signal TACT and the fuse activating signal FACT to the internal circuits to adjust the characteristics as a test mode signal TM. That is, the test mode signal TM is activated when any one of the test activating signal TACT and fuse activating signal FACT is activated. And, in the internal circuits, the connections are changed upon the activation of the test mode signal TM, wherein the internal timing and internal voltage are finely adjusted. Also, in order for the timing of a certain control signal to be caused to slip by +0.1 ns or +0.2 ns, the adjustment circuit
6
will be required, respectively.
In the test process, a probing test is carried out after a wafer is completed. The electric characteristics of respective chips are evaluated. At this time, for chips not having enough margins in the characteristics compared to the specifications, a trimming test is carried out. In the trimming test, the above-mentioned plurality of adjustment circuits
6
are actuated one after another, how and which internal circuits are adjusted are confirmed with respect to that the chips will have characteristics such that they can be shipped. After that, in the fuse process, a fuse formed in an adjustment circuit
6
for which activation is required is blown. The adjustment circuit
6
in which the fuse is blown normally activates the test mode signal TM. And, a chip is assembled in the assembling process, and the final test is carried out, wherein good chips are shipped.
Thus, by improving the characteristics of the internal circuits by the trimming, the yield can be remarkably increased.
However, in prior art adjustment circuits
6
, after the test mode signal TM was activated by the blowing of the fuse, the test mode signal TM could not be activated again. This is because there was no idea that the blown fuse is restored to its original state in order to relieve malfunction in the characteristics.
But, there are cases where the characteristics of shipped products are desired to be re-evaluated at the point of time when wafer is completed, in line with a decrease in the margin for action by high integration and high speed processing of semiconductor integrated circuits.
In such cases, in the prior arts, there was only a case where a mechanical means such as an FIB (Focused Ion Beam) processing apparatus is used. In the FIB processing apparatus, for example, a blown fuse can be re-connected, wherein the connections of wiring of control signals can be changed. However, in order to carry out FIB-process, a package that molds a chip can be drilled, and the chip surface must be exposed. Thus, the FIB process requires a particular technique including the pre-treatment. There was a problem by which a longer period of time is required.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a semiconductor integrated circuit that resets the characteristics of internal circuits after the characteristics thereof are adjusted by a ROM circuit formed of a fuse and such.
It is another object of the invention to provide a method for further adjusting the characteristics of internal circuits after the characteristics thereof are adjusted by a ROM circuit formed of a fuse and such, and in particular to provide a method for adjusting the characteristics of the internal circuits without destroying the semiconductor integrated circuit.
According to one of the aspects of the semiconductor integrated circuit of the invention, the semiconductor integrated circuit comprises an adjustment control circuit, a ROM circuit, and a selecting circuit. The adjustment control circuit activates the first adjustment signal that adjusts the characteristic of an internal circuit in response to an adjustment signal from the exterior. The ROM circuit activates the second adjustment signal that adjusts the characteristic of the internal circuit when information to adjust the characteristics of the internal circuits is programmed. The selecting circuit outputs any one of the first adjustment signal and the second adjustment signal in response to a control signal. The characteristics of the internal circuits are adjusted in response to any one of the first adjustment signal and the second adjustment signal. Therefore, by means of the selecting circuit selecting the first adjustment signal, the second adjustment signal is masked. That is, at this time, the information programmed in the ROM circuit in advance is invalidated. Further, where no information is programmed in the ROM circuit, it is possible to adjust the characteristics of the internal circuits without programming the ROM circuit.
According to another aspect of the semiconductor integrated circuit of the invention, the semiconductor integrated circuit has a normal operation mode and a test mode. The adjustment control circuit is activated during the test mo
Kato Yoshiharu
Wakasugi Nobuyoshi
Arent Fox Kintner & Plotkin & Kahn, PLLC
Auduong Gene N.
Fujitsu Limited
Nelms David
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