Semiconductor integrated circuit and method and system for desig

Details Semiconductor integrated circuit and method and system for desig Semiconductor integrated circuit and method and system for desig

1991-09-17

1995-01-03

Pascal, Robert J.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257211, 437 51, 364488, 326 39, 326 41, 326101, H01L 2702

Patent

active

053789040

ABSTRACT:
An LSI layout design method is for placing on a chip a plurality of different master cells, each of which has a plurality of signal wiring conductors not connected to internal elements, for example, transistors, resistors and so on for realizing a certain logic function.

REFERENCES:
patent: 4742471 (1988-05-01), Yoffa et al.
patent: 5047949 (1991-09-01), Yamaguchi
Handbook of Integrated Circuit Applications, published Jun. 30, 1981 by Asakura Bookstore, edited by Takuo Sugano, pp. 42-43.

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