Semiconductor integrated circuit and manufacturing method theref

Details Semiconductor integrated circuit and manufacturing method theref Semiconductor integrated circuit and manufacturing method theref

1988-11-15

1990-02-06

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437919, 437 75, 437 31, 437 60, 148DIG14, 357 51, H01L 2704

Patent

active

048988391

ABSTRACT:
A method of manufacturing a semiconductor integrated circuit comprises the steps of: forming an epitaxial layer covering a semiconductor substrate and buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; forming a lower electrode region of an MIS type capacitor in one of the islands; forming a base region of a vertical bipolar transistor simultaneously with or independently from the lower electrode in another island; depositing a thin dielectric layer of the MIS type capacitor on a portion of the lower electrode region; thereafter selectively diffusing impurities into the surface layer of the base region so as to form an emitter region of the vertical bipolar transistor; and forming an upper electrode of the MIS type capacitor on the thin dielectric layer.

REFERENCES:
patent: 4377029 (1983-03-01), Ozawa
patent: 4505766 (1985-03-01), Nagumo et al.
patent: 4633291 (1986-12-01), Koyama
patent: 4732872 (1988-03-01), Komatsu

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