Semiconductor integrated circuit and evaluation method of...

Details Semiconductor integrated circuit and evaluation method of... Semiconductor integrated circuit and evaluation method of...

2006-09-12

2006-09-12

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

C714S735000

Reexamination Certificate

active

07106108

ABSTRACT:
An input circuit writes an expected value to one end of an evaluation wiring. A latch circuit latches a logic level of the other end of the evaluation wiring. A first switch circuit connects an output of the input circuit to the input of the latch circuit. A second switch circuit connects the output of the input circuit to the one end of the evaluation wiring. A third switch circuit connects the other end of the evaluation wiring to the input of the latch circuit. By turning on, off, and off the first to third switch circuits, respectively, the output of the input circuit is directly connected to only the input of the latch circuit. In this state, the input circuit writes an expected value, and a logic level is read from the latch circuit. Accordingly, failure of the evaluation wiring can be easily discriminated from other failure.

REFERENCES:
patent: 4689551 (1987-08-01), Ryan et al.
patent: 5162259 (1992-11-01), Kolar et al.
patent: 5621740 (1997-04-01), Kamada
patent: 6028431 (2000-02-01), Hashida
patent: 6865703 (2005-03-01), Shimomura et al.
patent: 6954083 (2005-10-01), Thornley et al.
patent: 09-306965 (1997-11-01), None

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