Semiconductor integrated circuit and decode circuit for memory

Details Semiconductor integrated circuit and decode circuit for memory Semiconductor integrated circuit and decode circuit for memory

1997-11-19

1999-10-19

Hoang, Huan

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365229, 326105, G11C 800

Patent

active

059700181

ABSTRACT:
In plural internal logic circuits, plural transistors having the same function are merged into a single merged transistor. This merged transistor is interposed between a ground and a virtual ground line connected with a ground node of an inverter included in each of the internal logic circuits, and has a threshold voltage higher than a threshold voltage of a transistor included in each inverter. The merged transistor is controlled in accordance with a block selecting signal. Since the merged transistor is merged among the internal logic circuits, its gate width can be set larger, resulting in attaining a high speed operation of each inverter. During a standby, a leakage current can be suppressed since the merged transistor is in an off-state. During an operation, a leakage current can be suppressed in an unselected circuit block since the merged transistor is in an off-state. Accordingly, while suppressing increase of the circuit area, the internal logic circuits can attain a high speed operation and a leakage current can be minimized during both a standby and an operation.

REFERENCES:
patent: 5675548 (1997-10-01), Yokoyama et al.
patent: 5680362 (1997-10-01), Parris et al.
patent: 5808500 (1998-09-01), Kalpakjian

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