Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-08-17
2002-10-01
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190
Reexamination Certificate
active
06459621
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit device, such as a flash memory or the like, and to a data processing system, such as a digital still camera, in which such a semiconductor integrated circuit device is employed.
An example of a flash memory device has been disclosed in the 1994 Symposium on VLSI Circuits, Direst of Technical Papers, pp. 61-62.
In this flash memory, a state in which the threshold voltage of each of the memory cells included in the flash memory is high, and a state in which the threshold voltage thereof is low, can be defined as, for example, an erased state and a written (programmed) state, respectively. In this case, writing can be performed after erase operations have been performed collectively in word line units, for example. Upon completion of erase and write operations, the application of pulse-shaped voltages and a verify operation are repeatedly performed until a desired threshold voltage is acquired so that a change in threshold voltage is not increased undesirably.
When the application and transition of the voltage from the threshold voltage in the erased state to the threshold voltage in the written state has been completed. it is difficult to vary the threshold voltage as the threshold voltage approaches the written state. Therefore, the application of the same pulse width will lead to a state in which only the verify operation is being performed even though the threshold voltage changes very little. Therefore, when it is desired to perform writing using a fixed write voltage level, the pulse width is made long as the threshold voltage approaches the written state. The voltage may be gradually increased as an alternative to the gradual increase in pulse width.
High-accuracy writing has heretofore been realized so that a write level (equivalent to a verify word line voltage at writing) is set as, for example, 1.5V with respect to a power source voltage Vcc of, for example, 3.3V, and a write pulse or the threshold voltage of each memory cell varies over a range from 0.1V to 0.2V.
SUMMARY OF THE INVENTION
With respect to a power source voltage of, for example, 3.3V, a write level has heretofore been set practically to, for example, 1.5V, corresponding to about one half the power source voltage. One obtained by adding a difference in threshold voltage, for obtaining a current difference required to detect the voltage using a sense amplifier, to the voltage is defined as the minimum or lowest voltage (Vev) in an erased state. Upon erasing, the application of an erase pulse is controlled by detecting whether or not the threshold voltage of each memory cell has reached above Vev. A low voltage operation and high reliability can be achieved by lowering the write voltage and thereby reducing Vev to as low a level as possible.
However, the actual circumstances or fact is that the characteristic of each memory cell is varied by about three digits in the time required to reach a threshold voltage leading from an erased state to a written state when voltages to be applied upon writing are the same. When the writing of data into the corresponding memory cell is performed under such a condition, there may be cases where the threshold voltage results in 0V or less according to memory cells in the case of normal variations in characteristic of each memory cell unless a change in threshold voltage of the memory cell is set as a write pulse (width or voltage) that reaches 0.2V or less. The 3-digit variation results in about 3V if converted into a variation in equivalent threshold voltage. Thus, since the amount of change in threshold voltage per write pulse is equivalent to a change of 0.2V until the threshold voltage of a memory cell latest in written state reaches a written state, since the threshold voltage of a memory cell shortest in time required to bring it into the written state has led to the written state, it is necessary to apply a pulse 15 times if calculated simply. It is necessary to perform a verify operation for making a decision as to whether the threshold voltage has reached a desired value for each pulse. This has led to a lengthy overhead during the write time.
An object of the present invention is to speed up a write operation made to a non-volatile memory cell.
Another object of the present invention is to make the speeding up of a write operation made to a non-volatile memory cell compatible with a high reliability of data retention.
The above and other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical features disclosed in the present application will be described briefly as follows.
Namely, a semiconductor integrated circuit, such as a flash memory device, has a plurality of electrically erasable and programmable non-volatile memory cells and includes a control means for supplying a pulse-shaped voltage to each non-volatile memory cell until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control means has a first operating mode in which the amount of change in threshold voltage of each non-volatile memory cell, which varies each time the pulse-shaped voltage is applied thereto, is relatively large, and a second operating mode in which the amount of change in threshold voltage thereof is relatively small.
The amount of change in threshold voltage of each memory cell per pulse in a write voltage pulse or write voltage pulse train in a first operating mode (coarse write) and the amount of change in threshold voltage per pulse in a second operating mode (high-accuracy write) are defined as &Dgr;Vth
1
and &Dgr;Vth
2
, for example, respectively. considering at this time where the difference (cell window) in voltage between the minimum threshold corresponding to an erased state in a threshold voltage distribution of a non-volatile memory cell and the maximum threshold corresponding to a written state in the threshold voltage distribution is fixed, then the number of pulses required to change the threshold voltage of each memory cell at &Dgr;Vth
1
is smaller than that at &Dgr;Vth
2
. Therefore, the number of verify operations at the time that the first operating mode (&Dgr;Vth
1
) is used, is smaller than when the second operating mode (&Dgr;Vth
2
) is used. The time required to perform writing corresponds to the sum of the time required to change the threshold voltage of each memory cell itself and an overhead time,such as the time required to perform the verify operation. Thus, since a decrease in the number of verify operations results in a reduction in overhead, the write operation is speeded up as a whole.
It is desirable for the level (threshold voltage) to be written into a memory cell in the first operating mode to be higher than that in the second operating mode. Namely, a threshold voltage distribution in a written state,at &Dgr;Vth
1
in which the amount of change in threshold voltage is relatively large, becomes greater than a threshold voltage distribution in a written state at &Dgr;Vth
2
in the second operating mode. Thus, doing so is desired to avoid depleting. In other words, it is desired that a write verify voltage in the first operating mode (coarse write) be set higher than a write verify voltage in the second operating mode (high-accuracy write). Even if the cell window in the first operating mode is not set equal to that in the second operating mode, an erase level written into a memory cell in the first operating mode has a tendency to become higher than an erase level written into a memory cell in the second operating mode. Thus, the electric field between a floating gate and a semiconductor substrate of the memory cell written in the second write operating mode is lower than that of the memory cell written in the first operating mode at the time of information retention. Further, the information retention time of the memory cell written in the second write operat
Kawahara Takayuki
Kimura Katsutaka
Kotani Hiroaki
Kubono Shoji
Noda Satoshi
Antonelli, Terry Stout & Kraus, LLP.
Hitachi , Ltd.
Tran M.
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