Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-12-04
2004-08-17
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S111000, C327S081000
Reexamination Certificate
active
06777997
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit technique for addressing increase in speed of external output operation synchronized with a clock signal. More particularly, the invention relates to, for example, a semiconductor integrated circuit using, in an external interface portion, a MOS transistor having a breakdown voltage higher than that of an internal circuit and, further, to a technique effective to be applied to a burn-in method of such a semiconductor integrated circuit.
Japanese Unexamined Patent Application No. 9(1996)-8632 discloses a technique of stepping down an external power supply voltage within an LSI and making an external interface circuit operate with an external power supply voltage by using the stepped-down voltage as an operation power source of an internal circuit from a viewpoint of reduction in the size of a circuit device, reduction in power consumption, and the like. Japanese Unexamined Patent Application No. 2000-353947 discloses a technique in a semiconductor output circuit having a function of shifting the level of an internal signal to a signal level of a breakdown voltage of a semiconductor device or higher and outputting the resultant, and a function of outputting a signal at the internal signal level which is before the level shifting. In the semiconductor output circuit, for an output buffer in which a MOS transistor for protection used to increase a breakdown voltage between the gate and source of an output buffer transistor is provided on the power supply side, in order to prevent delay in speed of change in rising of a signal caused by on-state resistance of the MOS transistor for protection (the power supply voltage of the output buffer is the same as that in the internal circuit), the on-state resistance of the MOS transistor for protection is set to be varied by controlling a gate voltage.
SUMMARY OF THE INVENTION
In the conventional techniques, however, attention is not paid to delay in the output operation due to the level shifting function and, further, delay in external output operation due to propagation delay in a clock signal with respect to the point of addressing increase in the speed of external output operation synchronized with a clock signal. The inventor herein has examined the following points with respect to the point of addressing increase in speed of the external output operation synchronized with a clock signal.
First, the output operation delay due to the level shifting function was examined. For example, a semiconductor integrated circuit after a 0.35 &mgr;m process internally uses an MOS transistor having a low breakdown voltage and uses a MOS transistor of a high breakdown voltage in an interface portion with the outside. To operate an internal circuit with a low voltage such as 3.3V and operate the interface portion with a high voltage like 5.0V, a level shift circuit for shifting a low-voltage amplitude to a high-voltage amplitude is inserted between the internal circuit and an input/output buffer. If a low-voltage power is supplied to both of the internal circuit and the interface portion, the whole semiconductor integrated circuit can operate with a low voltage. The inventor herein has therefore examined to mount a host interface module for an LPC (Low Pin Count) bus interface as a parallel interface in a PC (Personal Computer) (hereinbelow, also simply called an LPC module) on such a semiconductor integrated circuit. In a high-speed host interface specification such as the LPC, bus wiring is suppressed and, in addition, data communication is performed synchronously with a PCI (Peripheral Component Interconnect) clock of 33 MHz (external clock signal). Consequently, designing which is tighter with respect to signal propagation delay in a semiconductor integrated circuit is demanded. Regarding an external power supply as well, a small signal amplitude is realized by using a low-voltage power supply of 3.3V or the like. However, the inventor herein has found that delay in a data output timing from an external clock signal is increased by the output operation delay due to the level shift circuit and the propagation delay of the internal clock.
The inventor herein has consequently examined, against the output operation delay due to the level shift circuit, a countermeasure of bypassing the level shift circuit by master slice of a wiring layer since both of the internal circuit and the interface portion operate with only a low voltage in the case of assuring the operation of the LPC module. However, when the interface portion is operated with a high voltage such as 7.0V and the internal circuit is operated with a low voltage such as 4.6V in order to apply a high voltage to the MOS transistor having a high breakdown voltage at the time of burn-in, the level shifting function is not realized in the bypassed portion. Therefore, an intermediate potential is applied to a circuit like an inverter or clocked inverter which receives a small-amplitude signal and a shoot-through current flows in the interface portion. The shoot-through current causes shifting of a threshold voltage of a MOS transistor by hot carriers and destruction of a MOS transistor.
When a low voltage of about 4.6V is applied to both of the internal circuit and the interface portion at the time of burn-in, the problem does not occur. However, a sufficient voltage stress cannot be put on a MOS transistor having a high breakdown voltage, so that an initial failure cannot be found, and the possibility that the failure becomes apparent in the market after shipment becomes high. It is therefore unavoidable that reliability deteriorates. An external terminal for an LPC module is conformed with a PCI bus and is used in an environment where there is no termination using a reflection wave. In the worst case, a voltage twice as high as the power supply voltage is applied to the terminal. Consequently, the MOS transistor in the interface portion to be connected to the terminal is requested to have a high breakdown voltage.
Second, the external output operation delay due to the propagation delay of the clock signal was examined. For example, in an LPC module, output data has to be determined within predetermined permissible delay time since a rising change of a PCI clock of 33 MHz (external clock signal). It was found out by the inventor herein that, when the permissible delay time is shortened, if a clock signal generated by an internal CPG (Clock Pulse Generator) is used as a latch clock signal for data output, the output data may not be determined within the time.
An object of the present invention is to provide a semiconductor integrated circuit capable of realizing higher-speed external output operation synchronized with a clock signal from the viewpoints of prevention of the output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer.
Another object of the invention is to provide a semiconductor integrated circuit capable of realizing higher-speed external output operation synchronized with an external clock signal from the viewpoint of suppression of clock delay.
Further another object of the invention is to provide a burn-in method capable of improving reliability of burn-in in a semiconductor integrated circuit with higher speed of an external output operation synchronized with a clock from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer.
The above and other objects and novel features of the invention will become apparent from the description of the specification and the appended drawings.
The outline of representative ones of inventions disclosed in the specification will be briefly described as follows.
(1) A semiconductor integrated circuit of the invention achieved from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer includes a first circuit (
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Katagiri Daisuke
Oshiba Masashi
Shimanuki Takeshi
Tahara Shigemitsu
Cunningham Terry D.
Miles & Stockbridge P.C.
Renesas Technology Corp.
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