Static information storage and retrieval – Powering
Reexamination Certificate
2001-02-01
2003-04-15
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Powering
C365S189050, C365S189090
Reexamination Certificate
active
06549480
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a configuration for measuring an internal voltage generated internal to a semiconductor integrated circuit and for applying externally a voltage for estimation. More particularly, the invention relates to a configuration for estimating an internal voltage in a semiconductor memory device.
2. Description of the Background Art
In a semiconductor integrated circuit, a voltage at a desired voltage level is generated for reduction in number of pins, reduction in power consumption of a whole system, and others.
FIG. 23
is a diagram schematically showing the whole configuration of a nonvolatile semiconductor memory device as an example of such a semiconductor integrated circuit. In
FIG. 23
, a nonvolatile semiconductor memory device
900
includes: a memory array
901
having a plurality of nonvolatile memory cells arranged in rows and columns; an X decoder
902
for selecting a row in the memory array
901
; a data register
903
for holding data of nonvolatile memory cells in one row in the memory array
901
; an X address buffer
904
for buffering a received X address signal and supplying the buffered signal to the X decoder
902
; a Y decoder
905
for decoding a received Y address signal and generating a column selection signal; and a Y gate
906
for selecting a register circuit included in the data register
903
in accordance with the column selection signal from the Y decoder
905
.
In the data register
903
, the register circuits are provided in correspondence with nonvolatile memory cells of one row in the memory array
901
. At the time of writing, write data is sequentially stored in the register circuits in the data register
903
. At the time of reading, data read from the nonvolatile memory cells in a selected row is held in the data register
903
.
The nonvolatile semiconductor memory device
900
further includes: a data output buffer
910
and an address/data input buffer
911
which are coupled to a data/address terminal (pad) group
917
; a write data input driver
908
for generating internal write data in accordance with write data applied from the address/data input buffer
911
and applying the internal write data to the Y gate
906
in a data writing operation mode; a Y address counter
907
for performing a counting operation with the Y address signal received from the address/data input buffer
911
being an initial value, sequentially shifting the Y address, and supplying a resultant Y address signal to the Y decoder
905
; and a read data output amplifier
909
for amplifying read data selected by the Y gate
906
and applying resultant data to the data output buffer
910
.
In the nonvolatile semiconductor memory device, data and an address are transferred via the data/address terminal group
917
. In applying a command for instructing an operation mode, a command and an address signal are simultaneously supplied to a data terminal and an address terminal in the data/address terminal group
917
. Thereafter, in writing data, write data is supplied to the data terminal in the data/address terminal group
917
.
FIG. 23
shows a case where 8-bit data DQ<
7
:
0
> is inputted and outputted as an example.
The nonvolatile semiconductor memory device
900
further includes: an OE buffer
919
for buffering an output enable signal OE applied via an input terminal (hereinafter, called a pad)
918
for application to the address/data input buffer
911
and a command decoder
912
; a CE buffer
921
for buffering a chip enable signal CE supplied via a pad
920
for application to the address/data input buffer
911
, the data output buffer
910
, and the command decoder
912
; a WE buffer
923
for buffering a write enable signal WE applied to the pad
920
for application to the command decoder
912
; an RES buffer
925
for buffering a reset signal RES applied to a pad
924
for application to the signal to the command decoder
912
; a buffer
927
for buffering a signal (external arbitrary signal other than the above signals) ETC for application to the command decoder
912
; and an SC buffer
929
for buffering a shift clock signal SC applied to a pad
928
for application to the Y address counter
907
.
An internal output enable signal from the OE buffer
919
is applied to the data output buffer
910
. When the output enable signal OE is made active, the data output buffer
910
is activated and applies data received from the read data output amplifier
909
to the pad group
917
. The chip enable signal CE attains an active state, to designate that the nonvolatile semiconductor memory device
900
is selected and a data access is performed. The data access means writing, reading and erasing operations. In accordance with the internal signals from the buffers
919
,
921
,
923
,
925
, and
927
, the command decoder
912
decodes a command applied from the address/data input buffer
911
and generates an operation mode instruction signal instructing a designated operation mode.
The nonvolatile semiconductor memory device
900
further includes: a read/write/erase control circuit
913
for performing a control for executing the designated operation in response to the operation mode instruction signal from the command decoder
912
; a reference voltage generating circuit
914
for generating reference voltages Vref
1
and Vref
2
at predetermined voltage levels under the control of the read/write/erase control circuit
913
; a high voltage generating circuit
915
for generating positive high voltages VPP
1
and VPP
2
necessary for programming/erasing data under the control of the read/write/erase control circuit
913
; and a high voltage generating circuit
916
for generating negative high voltages VNN
1
and VNN
2
under the control of the read/write/erase control circuit
913
.
In
FIG. 23
, the high voltages VPP
1
, VPP
2
, VNN
1
and VNN
2
from the high voltage generating circuits
915
and
916
are shown being applied to the X decoder
902
. The high voltages may be, however, transmitted to a bit line (memory cell column) via the Y gate
906
or may be applied to a substrate region in the memory array
901
. The nonvolatile memory cell is constructed by a stack gate type field effect transistor having a floating gate and a control gate. Data is stored in accordance with an accumulation amount of charges in the floating gate.
At the time of injecting electrons to the floating gate, a positive high voltage is applied to the control gate, and a ground voltage or a negative high voltage is applied to the substrate region or drain region (bit line). In injecting electrons to the floating gate, channel hot electrons (CHE) injection or injection of electrons by an FN (Fouler-Nordheim) tunneling current is performed. The injection method differs according to the configuration of the nonvolatile semiconductor memory device. On the other hand, in the case of ejecting electrons from the floating gate of the nonvolatile memory cell, the negative high voltage or ground voltage is applied to the control gate, and the positive high voltage or ground voltage is applied to the drain or the substrate region. The voltage level of the high voltage to be used differs according to the operation modes. A high voltage at a necessary voltage level is generated from the high voltage generating circuits
915
and
916
for each of the operation modes.
Each of the high voltage generating circuits
915
and
916
determines the level of a high voltage to be generated, according to the reference voltages Vref
1
and Vref
2
from the reference voltage generating circuit
914
. For example, such a adjusting scheme is employed that the high voltage VPP
1
is voltage-divided and the divided voltage level is made equal to the level of the reference voltage Vref
1
. The high voltage generating circuit
915
determines the voltage level of the high voltage VPP
1
. For the negative high voltages VNN
1
and VNN
2
, the voltage level
Dohi Yoshitsugu
Hosogane Akira
Nakai Hiroaki
Saeki Tatsuya
Hur Jung H.
Lebentritt Michael S.
Mitsubishi Denki & Kabushiki Kaisha
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