Semiconductor integrated circuit

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36523006, G11C 700

Patent

active

059149051

ABSTRACT:
A semiconductor integrated circuit having a decoder for decoding a first signal supplied thereto and having a plurality of bits and outputting a second signal in which only a predetermined bit of the plurality of bits of the first signal is set at active level, and an internal circuit for, in an ordinary operation mode in which a standby signal is at first level, performing a predetermined processing operation in response to the second signal decoded by said decoder and, in a standby mode in which the standby signal is at second level, stopping the predetermined processing operation to be set in a low power consumption state, comprising a signal level fixing circuit for, when the standby signal is at second level, fixing the predetermined bit of the plurality of bits of the first signal at predetermined level, and supplying a resultant signal to said decoder.

REFERENCES:
patent: 4970694 (1990-11-01), Tanaka et al.
patent: 5208781 (1993-05-01), Matsushima
patent: 5301144 (1994-04-01), Kohno
patent: 5712823 (1998-01-01), Gillingham

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