Boots – shoes – and leggings
Patent
1982-12-29
1986-04-15
Gruber, Felix D.
Boots, shoes, and leggings
364490, 365200, 371 10, 371 25, G06F 1130, G11C 1140, G01R 19165
Patent
active
045831793
ABSTRACT:
A semiconductor integrated circuit which includes therein at least one inspection circuit for inspecting a voltage level produced at an internal node to be inspected. The inspection circuit has at least a control signal input portion connected to the internal node to be inspected and an input part connected to an external input/output pin. The inspection circuit includes a series-connected transistor and diode connected between a power source and the input portion, a capacitor connected between a gate of the transistor and the input portion, and a transfer gate transistor connected between the control signal input portion and the gate of the transistor. The inspection circuit discriminates the level at the internal node according to a flow or nonflow of a current, via the external input/output pin, when a particular signal having a voltage level higher than the power source level is supplied to the external input/output pin.
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IEEE International Solid-State Circuits Conference, "Memories and Redundancy Techniques", by K. D. Wise, ISSCC 81, Session VIII, Feb. 18, 1981, pp. 79-85.
IBM Technical Disclosure Bulletin, "Maximized LSSD Test I/O Pin Usage", by W. P. Whitley, vol. 24, No. 2, Jul. 1981, pp. 1193-1194.
Horii Takashi
Nakano Masao
Nakano Tomio
Ogawa Junji
Tsuge Norihisa
Fujitsu Limited
Gruber Felix D.
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