Semiconductor integrated circuit

Static information storage and retrieval – Addressing – Sync/clocking

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Details

365220, 365239, G11C 800

Patent

active

054228581

ABSTRACT:
A rate conversion circuit area (8) is provided between a spread gate area (4) which operates in synchronization with a clock signal CLK and a RAM core (7) (macro cell) operating in synchronization with a clock signal (ck) whose frequency is higher than that of the clock signal (CLK). With this arrangement, the single port core is made accessible as a dual port RAM by forming the clock signal (ck) whose frequency is multiplied an optional number of times that of the clock signal (CLK), receiving access data equivalent to a plurality of operating cycles in parallel from the spread gate area during a predetermined unit operating access cycle period in the spread gate area, and serially supplying these to the RAM core 7 during the plurality of operating cycle periods in synchronization with the clock signal (ck).

REFERENCES:
patent: 4141039 (1979-02-01), Yamamoto
patent: 4945518 (1990-07-01), Muramatsu et al.
patent: 5046051 (1991-09-01), Doornhein et al.
patent: 5086388 (1992-02-01), Matoba et al.
patent: 5097447 (1992-03-01), Ogawa et al.

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