Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2006-07-31
2011-11-29
Hiltunen, Thomas J (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000
Reexamination Certificate
active
08067976
ABSTRACT:
A semiconductor integrated circuit (1) comprises a substrate voltage control circuit (10A), a drain current adjuster (E1), a MOS device characteristic detection circuit (20), and a drain current compensator (E2). The substrate voltage control circuit (10A) has at least one substrate voltage supply MOS device (m1) for controlling the supply of the substrate voltage of the semiconductor integrated circuit (1). The drain current adjuster (E1) adjusts the drain current of the substrate voltage supply MOS device (m1) by controlling the substrate voltage of the substrate voltage supply MOS device (m1). The MOS device characteristic detection circuit (20) has a characteristic detection device (m2) for detecting the characteristics of the substrate voltage supply MOS device (m1). The drain current compensator (E2) corrects the drain current of the substrate voltage supply MOS device (m1) by controlling the substrate voltage of the substrate voltage supply MOS device (m1) according to the characteristics of the substrate voltage supply MOS device (m1) detected by the MOS device characteristic detection circuit (20).
REFERENCES:
patent: 5682118 (1997-10-01), Kaenel et al.
patent: 6147508 (2000-11-01), Beck et al.
patent: 6784744 (2004-08-01), Tichauer
patent: 7106128 (2006-09-01), Tschanz et al.
patent: 7501880 (2009-03-01), Bonaccio et al.
patent: 7504876 (2009-03-01), Raghavan et al.
patent: 7514953 (2009-04-01), Perisetty
patent: 7564296 (2009-07-01), Ito
patent: 7746160 (2010-06-01), Raghavan et al.
patent: 7796073 (2010-09-01), Ogawa et al.
patent: 7816936 (2010-10-01), Ito
patent: 2004/0135621 (2004-07-01), Sumita et al.
patent: 2005/0116765 (2005-06-01), Sakiyama et al.
patent: 2006/0125550 (2006-06-01), Sumita et al.
patent: 2006/0125551 (2006-06-01), Sumita et al.
patent: 2010/0097128 (2010-04-01), Sumita
patent: 2004-165649 (2004-06-01), None
patent: 2005-197411 (2005-07-01), None
Sumita, M., et al., “Mixed Body-Bias Techniques with Fixed Vtand IdsGeneration Circuits,” ISSCC Digest of Technical Papers, Feb. 2004, 10 pages 0-7803-8267-6/04, 2004 IEEE International Solid-State Circuits Conference, IEEE.
Tschanz, J., et al., “Adaptive Body Bias for Reducing Impacts of Die-to Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage,” ISSCC Digest of Technical Papers, Feb. 2002, 3 pages 0-7803-7335-9, 2002 IEEE International Solid-State Circuits Conference, IEEE.
Hiltunen Thomas J
McDermott Will & Emery LLP
Panasonic Corporation
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