Semiconductor integrated circuit

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections

Reexamination Certificate

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Details

C257S773000, C257SE21583

Reexamination Certificate

active

07541625

ABSTRACT:
When dummy patterns are arranged to planarize LSI layout patterns, a plurality of dummy patterns1are arranged in a wiring layer in which signal wiring patterns2are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns2. These dummy patterns1cross signal wiring patterns3formed in another vertically adjacent wiring layer to have an inclination angle of generally 45 degrees. A plurality of dummy patterns13are located in the wiring layer in which the signal wiring patterns3are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns3. The dummy patterns1formed in one of the adjacent wiring layers cross the dummy patterns13formed in the other wiring layer at an angle of generally 90 degrees. This reduces fluctuations in wiring capacitance and equalizes fluctuations in the wiring capacitance to the maximum extent.

REFERENCES:
patent: 4903344 (1990-02-01), Inoue
patent: 6693315 (2004-02-01), Kuroda et al.
patent: 2004/0188849 (2004-09-01), Suga
patent: 2005/0023568 (2005-02-01), Nishimura
patent: 06-061230 (1994-03-01), None
patent: 10-125681 (1998-05-01), None
patent: 11-067918 (1999-03-01), None
patent: 2002-158278 (2002-05-01), None
patent: 2002-231815 (2002-08-01), None
patent: 2003-282569 (2003-10-01), None
patent: 2004-296864 (2004-10-01), None
patent: 2005-057003 (2005-03-01), None

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