Semiconductor integrated circuit

Static information storage and retrieval – Powering – Conservation of power

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365226, 365229, G11C 700

Patent

active

059333847

ABSTRACT:
In serially connected first and third inverters, the high-level-side source nodes are connected to a first pseudo-power supply line and the low-level-side source nodes are connected to a third pseudo-power supply line. In serially connected second and fourth inverters, the high-level-side source nodes are connected to a second pseudo-power supply line and the low-level-side source nodes are connected to a fourth pseudo-power supply line. The source nodes of transistors which are cut off in the operation mode, are disconnected from the power supply when first to fourth switch transistors are turned off according to an input signal, and these source nodes are short-circuited when either of fifth and sixth switch transistors is turned on.

REFERENCES:
patent: 5410278 (1995-04-01), Itoh et al.
patent: 5726946 (1998-03-01), Yamagata et al.

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