Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-02-06
2007-02-06
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189011, C345S098000, C345S099000, C345S100000, C345S531000
Reexamination Certificate
active
10798977
ABSTRACT:
A semiconductor integrated circuit is provided, using a one-port memory cell, capable of smoothly performing a data write/read operation in accordance with an instruction from a CPU and a data read operation to display an image on a display panel. The semiconductor integrated circuit includes a memory cell having a port through which data is input to and output from a set of bit lines, a write/read circuit connected with the port via the set of bit lines, a read circuit connected with the port via the set of bit lines, a CPU-system control circuit that controls the write/read circuit so that a data write or read operation based on a write request or read request from a CPU is performed for a first period, and a display-system control circuit that controls the read circuit so that data to be supplied to a display panel is read for a second period which does not overlap the first period.
REFERENCES:
patent: 6724378 (2004-04-01), Tamura et al.
patent: 6915400 (2005-07-01), Engelahardt
patent: 6933915 (2005-08-01), Hidaka et al.
patent: 2002/0186213 (2002-12-01), Koizumi
patent: 2002-014659 (2002-01-01), None
Harness & Dickey & Pierce P.L.C.
Nguyen Van-Thu
Seiko Epson Corporation
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