Static information storage and retrieval – Addressing – Sync/clocking
Patent
1998-12-08
2000-02-29
Le, Vu A.
Static information storage and retrieval
Addressing
Sync/clocking
36523008, G11C 700
Patent
active
060317884
ABSTRACT:
A semiconductor integrated circuit is adapted to make invalid an external clock, externally supplied to the semiconductor integrated circuit, when the semiconductor integrated circuit is set in an active power-down state. The semiconductor integrated circuit includes a delay locked loop DLL circuit which outputs an internal clock which phase is synchronized to the external clock. A latch circuit retains control signals in synchronism with the internal clock output by the DLL circuit. An internal circuit performs a predetermined process based on the control signals supplied from the latch circuit.
REFERENCES:
patent: 5315552 (1994-05-01), Yoneda
patent: 5406520 (1995-04-01), Tay
Bando Yoshihide
Taniguchi Nobutaka
Tomita Hiroyoshi
Fujitsu Limited
Le Vu A.
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