Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-02-23

2004-02-17

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

06693448

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the technology of semiconductor integrated circuit, and particularly to a technique which is applied effectively to the measurement of leak current of a semiconductor integrated circuit, and more particularly to a technique which is useful for the measurement of leak current of a CMOS integrated circuit.
BACKGROUND ART
For the detection of short-circuiting or breakdown of the pn junction of a semiconductor integrated circuit and the detection of breakdown of the gate insulation film of MOSFET, a leak current which is caused by these events is measured. A CMOS circuit has no or very small load current in its inactive state, and accordingly the presence or absence of a leak current can be determined by applying a power voltage and measuring the load current.
However, due to the trend of the higher circuit integration, the lower threshold signal level and the higher chip temperature resulting from the lower operating voltage, the load current of MOSFET in the inactive state increases, making it difficult to discriminate a leak current, and consequently it becomes difficult to measure the leak current accurately by the conventional manner based on the power voltage application and load current measurement.
Japanese Patent Unexamined Publication No.Hei 9 (1997)-101347 describes an invention which resembles and precedes the present invention.
FIG. 11
shows the representative of the embodiments of this preceding invention, which is intended to find a circuit having a leak current based on the circuit arrangement as follows. The internal circuit is segmented into multiple blocks, and the blocks (inner circuits
01
-
05
) are provided on their power voltage V
DD
side with switching MOSFETs S
1
-S
5
which can be turned on or off selectively by the control signals received on the external terminals (pads) P
1
-P
5
. The blocks (inner circuits
01
-
05
) are further provided on their ground voltage GND side with a leak current lead-out circuit
21
, which is formed of a transistor
27
and a current mirror circuit (
29
,
31
), for shutting off the load current of the inner circuits at the detection of leak current. The circuit arrangement includes a leak current detecting circuit which is formed of a reference current generation circuit
17
connected in series to one transistor of the current mirror circuit and an inverter
19
which is adapted to compare the leak current flowing through the leak current lead-out circuit
21
with the reference current provided by the reference current generation circuit
17
.
Although this preceding invention is capable of finding a circuit having a leak current, this “tandem circuit arrangement” having the MOS transistors connected on the power voltage V
DD
side and ground voltage GND side makes the supply oltage of the inner circuits lower than the power voltage on the chip terminal. On the other hand, a power voltage at a certain voltage level or higher is needed for the normal operation of the inner circuits. On this account, the circuit arrangement of this preceding invention cannot be fully adaptive to the trend of lower power voltage of semiconductor integrated circuits. Moreover, if the reference current generation circuit
17
or inverter
19
used in the leak current lead-out circuit and leak current detecting circuit fails, a leak current cannot be detected or will be detected erroneously.
Although this preceding invention also shows an embodiment (
FIG. 11
of the above-mentioned patent publication) including a leak current detecting circuit for each segmented inner circuit, the leak current detecting circuit having two MOS transistors in tandem connection (
FIG. 12
of the above-mentioned patent publication) cannot be fully adaptive to the trend of lower power voltage of semiconductor integrated circuits.
It is an object of the present invention to provide a technique of semiconductor integrated circuit capable of detecting easily and accurately the presence or absence of a leak current in excess of the specified amount in a CMOS integrated circuit chip.
Another object of the present invention is to provide a technique of semiconductor integrated circuit capable of detecting a leak current even in the case of low-voltage design.
Still another object of the present invention is to provide a technique of semiconductor integrated circuit capable of detecting the abnormality of the leak current detecting circuit.


REFERENCES:
patent: 5097206 (1992-03-01), Perner
patent: 5592494 (1997-01-01), Nozuyama
patent: 6101623 (2000-08-01), Nozuyama
patent: 6144214 (2000-11-01), Athan
patent: 6151694 (2000-11-01), Nozuyama
patent: 03120859 (1991-05-01), None
patent: 04290975 (1992-10-01), None
patent: 05326870 (1993-12-01), None
patent: 07037956 (1995-02-01), None
patent: 09101347 (1997-04-01), None

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