Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2003-01-15

2004-08-10

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S019000

Reexamination Certificate

active

06774679

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit including a phase comparator circuit for detecting phase difference between two clock signals, and particularly to a semiconductor integrated circuit including a phase comparator circuit for a PLL (phase locked loop) or DLL (delay locked loop).
BACKGROUND ART
For example, in a reproducing circuit for reproducing recorded data or a receive circuit for receiving transmitted data, a PLL (phase locked loop) having a combination of a voltage controlled oscillator and a phase comparator circuit or a DLL (delay locked loop) having a combination of a voltage controlled delay element and a phase comparator circuit is used to generate a clock signal synchronized to input data.
The structure of a PLL circuit using a conventional phase comparator circuit is shown in FIG.
1
. This PLL circuit comprises a phase comparator circuit
1
for comparing a phase of a reference clock signal REF and a phase of a clock signal CLK to output an UP signal or a DOWN signal depending on the phase difference, a charge pump circuit
5
for supplying output current I
PDI
according to the UP signal and DOWN signal output from the phase comparator circuit
1
, a loop filter
6
, having low pass characteristics, for converting output current I
PDI
of the charge pump circuit
5
to a control voltage V
CTL
, and a VCO (voltage controlled oscillator)
7
oscillating at a frequency controlled by the control voltage V
CTL
to output a clock signal CLK.
The structure of the phase comparator circuit as shown in
FIG. 1
is shown in FIG.
2
. As shown in
FIG. 2
, the phase comparator circuit
1
comprises two flip flop circuits
11
and
12
and an AND circuit
13
.
A high level signal “
1
” is supplied to data input terminals D of the flip flop circuits
11
and
12
. The flip flop circuit
11
outputs a high level UP signal synchronized with the rising edge of the reference clock signal REF supplied to the clock input terminal CK, while the flip flop circuit
12
outputs a high level DOWN signal synchronized with the rising edge of the clock signal CLK supplied to the clock input terminal CK.
The AND circuit
13
provides a high level signal to the clear terminals CLR of the flip flop circuits
11
and
12
when both the UP signal and the DOWN signal become high levels. In this way, the flip flop circuits
11
and
12
are cleared and both the UP signal and the DOWN signal become low levels.
As a result, in the case where the phase of the clock signal CLK is delayed compared to the reference clock signal REF, the phase comparator circuit
1
outputs a high level UP signal from the rising edge of the reference clock signal REF to the rising edge of the clock signal CLK. On the other hand, if the phase of the clock signal CLK is advanced compared to the phase of the reference clock signal REF, the phase comparator circuit
1
outputs a high level DOWN signal from the rising edge of the clock signal CLK to the rising edge of the reference clock signal REF.
However, the minimum pulse width of the UP signal and the DOWN signal that can be output by the phase comparator circuit
1
is determined by the manufacturing technology used, and in the case where an absolute value of a phase difference between the clock signal CLK and the reference clock signal REF is less than that minimum pulse width, a dead zone exists where neither the UP signal or the DOWN signal are output.
FIG. 3
shows a relationship between phase difference between the two clock signals and output current of the charge pump circuit when a dead zone exists in the phase comparator circuit.
In order to eliminate the dead zone of the phase comparator circuit
1
, it has been considered to increase the delay time of the AND circuit
13
. If this is done, in the event that a phase difference between the clock signal CLK and the reference clock signal REF is small, a pulse is output for both the UP signal and the DOWN signal and the charge pump circuit
5
can supply output current I
PDI
based on the width of these pulses. However, with respect to operation of the charge pump circuit
5
, the following problems arise.
The structure of the charge pump circuit as shown in
FIG. 1
is shown in FIG.
4
. As shown in
FIG. 4
, the charge pump circuit
5
comprises an inverter
51
for inverting the UP signal, a P-channel transistor Q
1
for supplying electrical current based on the inverted UP signal, an N-channel transistor Q
2
for supplying electrical current based on the DOWN signal, and constant current sources
52
and
53
. Here, the constant current sources
52
and
53
normally stop operating as constant current sources if a voltage greater than or equal to a specified voltage is not applied. If the constant current sources
52
and
53
do not operate as constant current sources, it is not possible to correctly balance current in the transistors Q
1
and Q
2
.
Specifically, in the case where the transistor Q
1
operates close to the power source voltage V
DD
, a voltage applied to the constant current source
52
connected to transistor Q
1
becomes small, and therefore, current flowing when the transistor Q
1
is on becomes smaller than a steady value. Similarly, in the case where the transistor Q
2
operates close to the power source voltage V
SS
, a voltage applied to the constant current source
53
connected to transistor Q
2
becomes small, and therefore, current flowing when the transistor Q
2
is on becomes smaller than a steady value. In this way, in the event that the constant current sources
52
and
53
do not operate normally, then as shown in
FIG. 5
, at a position where the phase difference between the clock signal CLK and the reference clock signal REF becomes zero, the output current I
PDI
of the charge pump circuit
5
no longer becomes zero.
As described above, in the case where a dead zone exists in the characteristics of the phase comparator circuit, or where the constant current sources of the charge pump circuit do not operate normally even if there is no dead zone in the characteristic of the phase comparator circuit, there are problems such as jitter of the clock signal CLK becoming large and an offset arising in the phase of the clock signal CLK with respect to the reference clock signal REF.
DISCLOSURE OF THE INVENTION
In view of the above described situation, the object of the present invention is to improve overall lock precision of a PLL or DLL in a semiconductor integrated circuit including a phase comparator circuit for a PLL or DLL by preventing a dead zone of the phase comparator circuit and preventing output current offset of a charge pump circuit.
In order to achieve the above described object, a semiconductor integrated circuit according to the present invention comprises a first circuit for receiving a first clock signal and a second clock signal and for activating a first phase difference signal corresponding to a phase difference between the first clock signal and the second clock signal when a phase of the first clock signal is delayed by more than a predetermined value in comparison with a phase of the second clock signal and activating a second phase difference signal corresponding to the phase difference when the phase of the first clock signal is advanced by more than a predetermined value in comparison with the phase of the second clock signal, a second circuit for receiving the first clock signal and the second clock signal and for activating a first pulse signal when an edge of the first clock signal is delayed in comparison with an edge of the second clock signal and activating a second pulse signal when the edge of the first clock signal is advanced in comparison with the edge of the second clock signal, a third circuit for combining the first phase difference signal output from the first circuit and the first pulse signal output from the second circuit, and a fourth circuit for combining the second phase difference signal output from the first circuit and the second pulse signal output from the second circuit.
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