Static information storage and retrieval – Addressing – Sync/clocking
Patent
1991-06-27
1993-04-06
Popek, Joseph A.
Static information storage and retrieval
Addressing
Sync/clocking
36518905, 36523008, G11C 700
Patent
active
052009262
ABSTRACT:
A data transfer control circuit is connected between a sense amplifier and output buffer circuit. The data transfer control circuit is controlled by a pulse signal supplied from a pulse signal generator so as to have longer delay time which pulse signal is not generated by the pulse signal generator, and operate as noise canceller and prevents from outputting erroneous signal therefrom to the output buffer circuit.
REFERENCES:
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patent: 4707809 (1987-11-01), Ando
patent: 4827454 (1989-05-01), Okazaki
patent: 4959816 (1990-09-01), Iwahashi et al.
patent: 5056064 (1991-10-01), Iwahashi et al.
IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, T. Wada et al., "A 34 ns 1-Mbit CMOS SRAM Using Triple Polysilicon", pp. 727-732.
Iwahashi Hiroshi
Kato Hideo
Tatsumi Yuuichi
Kabushiki Kaisha Toshiba
Popek Joseph A.
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