Semiconductor integrated circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control

Reexamination Certificate

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Details

C327S544000, C327S403000, C327S404000, C326S080000, C326S081000

Reexamination Certificate

active

06677797

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-395932, filed Dec. 26, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit which has a plurality of power supply levels and causes logic circuits to operate on a very low power supply voltage, and more particularly to a semiconductor integrated circuit provided with an operating circuit and a standby circuit.
2. Description of the Related Art
In recent years, the packing density of semiconductor integrated circuits has increased remarkably. In semiconductor memory devices of the order of gigabits, hundreds of millions of semiconductor elements have been squeezed into a single chip. In a 64-bit microprocessor, millions of to tens of millions of semiconductor elements have been squeezed into a single chip. The improvement of the packing density has been achieved by the miniaturization of elements. In a 1-Gbit DRAM (Dynamic Random Access Memory), MOS transistors with a gate length of 0.15 &mgr;m have been used. In a DRAM with a much higher packing density, MOS transistors with a gate length of 0.1 &mgr;m or less will be used.
In such very small MOS transistors, the characteristics of the transistors deteriorate due to the generation of hot carriers, or the breakdown of the insulating films occurs due to TDDB (Time-Dependent Dielectric Breakdown). When the concentration of impurities in the substrate region or other regions is increased to suppress a drop in the threshold voltage due to the gate length getting shorter, the junction voltage of the source and drain drops.
To maintain the reliability of these fine elements, it is important to drop the power supply voltage. That is, the generation of hot carriers is prevented by weakening the horizontal electric field between the source and drain, and TDDB is prevented by weakening the vertical electric field between the gate and bulk. Moreover, dropping the power supply voltage decreases the reverse bias applied to the junction between the source and bulk and to the junction between the drain and bulk, thereby coping with a drop in the breakdown voltage.
In mobile information apparatus, whose market has been expanding rapidly in recent years, a lightweight power supply with a high energy density, such as a lithium ion battery, has been widely used. Since the voltage of the lithium ion battery is about 3 V, it is higher than the breakdown voltage of the very small MOS transistor. Therefore, when the lithium ion battery is applied to a circuit using very small transistors, it is necessary to drop its voltage using a DC-DC voltage converter. Since the power consumption of the CMOS circuit used in a logic circuit is proportional to the operating frequency and further proportional to the square of the power supply voltage, lowering the power supply voltage has a significant effect on the decrease of the chip power consumption.
Using mobile information apparatus for a longer time requires a battery with high energy density, a DC-DC converter with high efficiency, and an integrated circuit operating on a low voltage. From the viewpoint of reducing the power consumption of an LSI, it is desirable to use a stepped-down power supply voltage particularly in a microprocessor or baseband LSI which consumes a lot of power.
On the other hand, the mobile information apparatus requires memory elements, such as DRAMs or SRAMs (static random access memories) as well as the logic circuits. In DRAMs, the first subject is to secure a sufficient amount of charge in the cells to increase resistance to errors due to software. In SRAMs, the first subject is to avoid the deterioration of speed when they are operating on low power supply voltages. Therefore, in DRAMs and SRAMs, the power consumption has not been reduced remarkably as found in logic circuits. Presently, elements operating on a power supply voltage of about 1.5 V have been put to practical use.
The power supply voltage of about 1.5 V, however, is much higher than the lowest voltage on which the logic circuits can operate. For this reason, it is conceivable that an LSI including both memory circuits and logic circuits takes and will take a multi-power-supply configuration that supplies various power supply voltages according to each circuit section.
FIG. 1
shows a semiconductor integrated circuit for mobile information apparatus obtained by integrating a memory circuit and a logic circuit into a single chip and the configuration of its power supply. The power supply system is composed of a lithium ion battery
1700
and a DC-DC voltage converter
1701
. The semiconductor integrated circuit
1704
is composed of a logic circuit
1702
and an on-chip memory circuit
1703
.
More specifically, 3 V from the lithium ion battery
1700
is converted by the DC-DC voltage converter
1700
into a voltage of 0.5 V. The 0.5-V power supply is supplied to the logic circuit
1702
. On the other hand, since the on-chip memory circuit
1703
generally needs a power supply voltage of 1.5 to 2.0 V or higher for high speed operation, the 3-V power supply of the lithium ion battery
1700
is supplied to the memory circuit
1703
.
With the configuration of
FIG. 1
, dropping the power supply voltage of the logic circuit from 3 V to about 0.5 V enables the power consumption in operation to be decreased theoretically by about 95%, which reduces the power consumption dramatically.
However, when the power supply voltage of a CMOS circuit operating on a power supply voltage usually ranging from 3 V to 2 V is dropped, since the threshold voltage is high as it is, there arises a problem: the operating speed of the elements decreases or they do not operate.
To solve this problem, the threshold voltage of the MOS transistors is dropped as the power supply voltage drops. For example, to configure a logic circuit operating on a low power supply voltage of 0.5 V, it is necessary to use a MOSFET whose threshold voltage is about 0.1 to 0.15 V in absolute value, about one-third of the threshold voltage of a conventional MOSFET.
With such a low threshold voltage, however, if the S factor that determines the sub-threshold characteristic of, for example, a MOSFET is 100 mV/decade, the leakage current when the MOSFET is off increases significantly by about three orders of magnitude.
Consequently, in an approach of only lowering the power supply, the power consumption in operation can be decreased, whereas the power consumption in the standby state of the apparatus increases significantly. Therefore, the semiconductor integrated circuit is unsuitable for mobile information apparatus as it is.
FIG. 2
shows a known semiconductor integrated circuit configured to overcome the above problem. A power supply voltage converter
1801
converts 3 V from a lithium ion battery
1800
into a voltage of 0.5 V to supply the voltage as low as 0.5 V to a semiconductor integrated circuit
1805
including a logic circuit
1802
, thereby reducing the power consumption in operation.
The semiconductor integrated circuit
1805
further comprises a positive power supply voltage generator
1803
and a negative power supply voltage generator
1804
and generates a potential higher than the power supply voltage at the positive power supply voltage generator
1803
and a potential lower than the ground potential at the negative power supply voltage generator
1804
. The semiconductor integrated circuit is configured to supply the potentials generated at the voltage generators to the n-well and p-well (now shown) in the logic circuit
1802
, thereby making somewhat lower the absolute value of the threshold voltage of the MOSFET in the logic circuit in normal operation to give priority to the operating speed.
With the configuration of
FIG. 2
, the power consumption can be reduced by making larger the absolute value of the threshold voltage of the MOSFET in the logic circuit in

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