Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2001-06-06
2004-01-27
Toatley, Jr., Gregory J. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C323S268000
Reexamination Certificate
active
06683767
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit which incorporates voltage regulators for stepping down the externally-supplied power voltage, and to a technique which is applied effectively to data processing systems, such as portable information terminals, having their semiconductor chips required to be smaller in size and power consumption.
Among semiconductor integrated circuits having internal circuits which operate based on an internal power voltage (Vint: 1.8 V, 1.5 V, etc.) lower than an external power voltage (Vext: 3.3 V, 5.0 V, etc.), there are some integrated circuits having a voltage step-down circuit which steps down an external power voltage to produce an internal power voltage. With the intention of reducing the voltage drop of the internal power voltage caused by the parasitic resistance of wires from the voltage step-down circuit to the internal circuits, there is known a technique of building multiple voltage step-down circuits on the chip and laid near the power pads so that the voltage drop of the external power voltage caused by the parasitic resistance of the wires from the power pads to the voltage step-down circuits is reduced.
Publications pertinent to this technique include Japanese Patent Unexamined Publications No. Hei 9 (1997)-289288 and No. Hei 2 (1990)-224267.
SUMMARY OF THE INVENTION
The inventors of the present invention have studied these prior arts to find the following affairs.
The prior arts are designed to lay voltage step-down circuits near the power pads so as to minimize the voltage drop of the internal power voltage caused by the parasitic resistance of the wires from the voltage step-down circuits to the internal circuits and minimize the voltage drop of the external power voltage on the wires from the power pads to the voltage step-down circuits. However, these prior arts do not consider the increase of chip area due to the on-chip provision of the voltage step-down circuits and do not present clearly the scheme of reducing this overhead chip area.
The inventors of the present invention have contemplated to foster the reduction of power consumption by use of a step-down power voltage, and found that it is beneficial to control the step-down voltage level depending on the operational state of the semiconductor integrated circuit and use the step-down power voltage or external power voltage selectively in controlling the threshold voltage of MOS transistors by varying the substrate voltage for the reduction of sub-threshold leak current of the circuits which operate based on the step-down power voltage.
An object of the present invention is to provide a semiconductor integrated circuit which is capable of minimizing the increase of chip area caused by the on-chip provision of voltage regulators which step down the external power voltage and also stabilizing the step-down voltage.
Another object of the present invention is to provide a semiconductor integrated circuit which is capable of advancing the power conservation based on the use of step-down voltages.
Still another object of the present invention is to provide a technique which facilitates the design of semiconductor integrated circuits which are intended to minimize the increase of chip area caused by the on-chip provision of voltage regulators for stepping down the external power voltage and stabilize the step-down voltage.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Among the affairs of the present invention disclosed in this specification, representatives are briefed as follows.
(1) Buffer and Protection Circuit Area
The inventive semiconductor integrated circuit has on a semiconductor chip (
10
) a first area (
1
) for laying external terminals (
20
) such as the electrode pads for the input/output signals and power voltages. The first area (
1
) is adjoined by a second area (
2
) for laying buffers and protection circuits pertinent to the input/output signals and power voltages. The second area (
2
) is also used for laying multiple voltage regulators (
150
-
157
) which step down a first power voltage (Vext) supplied from the outside of the semiconductor chip (
10
) to produce at least one kind of internal power voltage (Vint) which is lower than Vext. The voltage regulators are laid in the area having its width generally determined from the layout width of buffers and protection circuits and at positions near the external terminals of the first power voltage and ground voltage. There is a third area for laying first internal circuits which operate based on the internal power voltage.
The portions of the second area near the external terminals of the first power voltage and ground voltage are not used to lay buffers, which are laid solely near the external terminals of signals, and accordingly these portions are inherently less crowded and readily available for the layout of voltage regulators. The buffers and protection circuits are basically provided for individual external terminals and they are smaller in number as compared with circuits in the whole semiconductor integrated circuit, and the area corresponding to the second area is conceived to be an area having a space where the voltage regulators can be formed.
By using the second area having its width generally determined from the layout width of buffers and protection circuits to lay multiple voltage regulators, it is relatively easy to increase the number of regulators without increasing the chip area proportionally. Accordingly, this layout scheme readily minimizes the increase of chip area due to the on-chip provision of voltage regulators which step down the external power voltage, and moreover achieves the stabilization of the step down voltage by allowing the supply of a large current to the first internal circuits.
(2) Main Power Line
The semiconductor integrated circuit has power lines including a main power line (L
20
) which is connected to the outputs of the voltage regulators for distributing the internal power voltage to the first internal circuits. Preferably, the main power line is formed to be a closed loop, so that the internal power voltage is constant throughout the power line and supplied stably to many scattering circuits located on the semiconductor chip.
The main power line is laid to have a generally equal parasitic resistance between output nodes of voltage regulators, so that the internal power voltage has an even voltage level throughout the line. This is attainable by making a generally equal distance between output nodes of voltage regulators on the main power line.
For coping with a limited area available for the voltage regulators to be integrated on the semiconductor chip, it is advantageous to adopt series voltage regulators, with a stabilizing capacitor (C
10
) being attached externally to the chip by the provision of an external terminal (
20
A-
2
) which is connected to the main power line.
(3) Signal Level Converting Circuit
In regard to the transfer of signals between a circuit which operates based on the first power voltage and a circuit which operates based on the internal power voltage, the former circuit can send the signal directly to the latter circuit. In another case of putting a signal from the latter circuit to the former circuit, the former circuit receives a signal level lower than the power voltage, for example, the input signal level of a CMOS circuit can be logically intermediate, causing possibly the creation of a undesired through-current. For preventing this event from occurring, second internal circuits which operate based on the first power voltage are provided with level converting circuits (G
3
) which convert the output signals of the first internal circuits to have logic levels derived from the first power voltage. Specifically, for example, a first logic circuit provides the output signal for a buffer in the second area via the level converting circuit.
(4) Reference Voltage Gen
Ashiga Koichi
Hiraki Mitsuru
Ito Takayasu
Benenson Boris
Hitachi , Ltd.
Miles & Stockbridge P.C.
Toatley , Jr. Gregory J.
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