Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-10-02

2004-09-07

DeBeradinis, Robert (Department: 2836)

Electrical transmission or interconnection systems

Plural supply circuits or sources

Substitute or emergency source

C307S066000, C307S140000

Reexamination Certificate

active

06787936

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit in which components such as a CPU, memory, clock generator circuit, and timer circuit are integrated on one silicon substrate, and a backup battery is provided outside this silicon substrate.
BACKGROUND OF THE INVENTION
Japanese Patent Application Laid-Open No. 4-127290 has disclosed the conventional art relative to a semiconductor integrated circuit having a backup battery provided outside a silicon substrate.
FIG. 4
shows the disclosed semiconductor integrated circuit. This conventional art shows an example of a non-contact IC card. This non-contact IC card transmits and receives signals to and from an external device in the form of electromagnetic waves. The IC card
100
includes the CPU
101
that controls entire operation of the IC card
100
. The CPU
101
is connected with the ROM
102
and RAM
103
via the bus
99
. Moreover, the bus
99
is connected with the input/output control circuit
104
that controls input/output to an external device. The input-output control circuit
104
is connected with the antenna
107
via the modulating/demodulating circuit
106
. The battery
108
supplies power to the CPU
101
, ROM
102
, RAM
103
, input/output control circuit
104
, modulating/demodulating circuit
106
, and the antenna
107
.
FIG. 5
shows an internal configuration of the battery
108
. The battery
108
comprises the constant voltage source
109
, power supervisory circuit
110
, diode
114
for rectification, and the capacitor
115
. The constant voltage source
109
generates a voltage VDD, and the power supervisory circuit
110
supervises the magnitude VDD of the voltage, and controls opening and closing of the switches
111
,
112
and
113
. The capacitor
115
is operated as a backup voltage source.
The IC card
100
receives a request signal in the form of electromagnetic waves via the antenna
107
from the external device. When such a request signal is received, the request signal is input into the CPU
101
via the modulating/demodulating circuit
106
. The CPU
101
decodes the request signal, and makes a predetermined answer signal based on program and data stored in the ROM
102
and the RAM
103
. The answer signal is modulated by the modulating/demodulating circuit
106
via the input/output control circuit
104
, and thereafter, is transmitted from the antenna
107
to the external device. When the above external output is performed, the CPU
101
rewrites the data stored in the RAM
103
in preparation for the next signal input from the external device. During a series of communication operation, the power supply voltage VDD is supplied from the battery
108
to these CPU
101
, ROM
102
, RAM
103
, input/output control circuit
104
, modulating/demodulating circuit
106
and antenna
107
. At that time, in the battery
108
, the switches
111
and
112
are connected individually to a terminal A side, and thereby, a constant voltage VDD generated by the constant voltage source
109
is supplied to the CPU
101
or the like. Further, at that time, the capacitor
115
is charged with a charge Q=C·VDD (C is capacity value).
In the above configuration, a power failure in the constant voltage source
109
causes unstable operation of various devices included in the IC card, such as CPU
101
, ROM
102
, and antenna
107
. Under such a state, if the communication operation is continued, there is a possibility that the IC card will fall into an unpredictable operating state; more specifically, the program may run away, and stop midway in communication.
In order to avoid this situation, in the battery
108
, a voltage level of the power supply voltage VDD is supervised by the power supervisory circuit
110
. When detecting that the power supply voltage VDD has become lower than a predetermined voltage, the power supervisory circuit
110
informs the CPU
101
of the detection result, and simultaneously, changes the switches
111
,
112
and
113
to a terminal B side. These switches
111
,
112
and
113
are changed to the terminal B-side, and thereby, the power supply voltage is supplied from the capacitor
115
to the CPU
101
, ROM
102
, RAM
103
, input/output control circuit
104
, modulating/demodulating circuit
106
and antenna
107
. Thereafter, various devices such as CPU
101
included in the IC card are operated by power from the capacitor
115
; therefore, it is possible to shift the IC card
100
to a state of receiving no external request signal (=sleep mode state) after the current communication operation is completed. As described above, the battery
108
is provided with the backup capacitor
115
, and thereby, even if the voltage of the constant voltage source
109
varies, it has no influence on the external device.
According to the conventional art, as described above, the backup capacitor
115
having a relatively large capacity has been connected to the power supply terminal. Therefore, even in the case where the power supply voltage of the constant voltage source
109
becomes lower than a predetermined voltage, it is possible to operate a micro-controller for a certain fixed time by using an electric energy stored in the backup capacitor
115
.
However, according to the conventional art, a power supply interconnect line of the constant voltage source
109
and a power supply interconnect line of the backup capacitor
115
are connected in common to the micro-controller (CPU
101
, ROM
102
, RAM
103
or the like). Further, these common power supply interconnect lines are connected with electronic elements such as modulating/demodulating circuit
106
, and antenna
107
except the micro-controller. Thus, according to the conventional art, in the backup, charge of the backup capacitor
115
is used for operating electronic elements, such as modulating/demodulating circuit
106
, and antenna
107
. For this reason, a problem arises such that micro-controller operable time becomes short. Further, according to the conventional art, in the micro-controller, the power supply interconnecting line is connected in common to all devices of the micro-controller. For this reason, when a voltage drop of the constant voltage source
109
is generated, even if the device to be actually operated is only one device (e.g., memory for storing data, timer circuit for counting time), all devices have been operated. As a result, a problem arises such that an operable time of various devices included in the micro-controller becomes short.
Further, according to the conventional art, the backup capacitor
115
charges a voltage of the constant voltage source
109
as it is; therefore, a charge Q stored in the backup capacitor
115
is the product of the power supply voltage VDD and the capacity value C of capacitor Q=Vcc·C. As a result, a problem arises such that a micro-controller operable time is limited by the capacity value C of the backup capacitor
115
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit, which can operate a micro-controller for a long time when power failure such as instantaneous blackout is generated.
The semiconductor integrated circuit according to one aspect of the present invention comprises a micro-controller having at least two electronic circuits; a power supervisory circuit for supervising a power supply voltage of externally provided main power source and backup power source; a first power supply terminal connected to the main power source; a second power supply terminal connected to the backup power source; a first power supply line connecting a first electronic circuit of the micro-controller and the first power supply terminal; and a second power supply line connecting a second electronic circuit of the micro-controller and the second power supply terminal. The power supervisory circuit is supplied with main power from the main power source through and first power supply terminal, and supplied with backup power from the backup power sourc

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