Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2001-06-07
2003-02-11
Vo, Peter (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S720000, C029S721000, C029S740000, C029S835000, C029S843000, C029S844000, C228S004500, C228S005100, C228S180500, C356S237100, C901S047000
Reexamination Certificate
active
06516515
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the manufacturing engineering of a semiconductor device, particularly relates to a bonding technique for bonding an inner lead laid on a carrier to an electrode pad formed on a semiconductor chip (hereinafter called chip) and, for example, relates to a bonding technique effective when utilized for a method of manufacturing a semiconductor integrated circuit (hereinafter called IC) provided with a chip-sized package or a chip scale package (hereinafter called CSP) in size equal to or approximately equal to the size of a chip.
As electronic equipment using ICs are miniaturized and thinned, the reduction of an IC package is desired. Various CSPs are developed to meet the above demand and, a micro ball grid array package (hereinafter called &mgr;BGA) constituted as follows is one example. That is, a tape carrier is mechanically connected on the main surface on the side of an electrode pad of a chip via an insulating film, each inner lead laid on the tape carrier is bonded to each electrode pad of the chip and a bump as each external terminal is soldered to each outer lead and protruded.
For a method of bonding an inner lead in &mgr;BGA, there is a single point bonding method (hereinafter called only bonding method) of successively welding multiple inner leads one at a time on each electrode pad arranged on the overall chip with pressure by a bonding tool.
CSP is described on pages 112 and 113 of a monthly, “Semiconductor World” published in May, 1995 by Press Journal.
For an example describing a method of bonding a memory chip to a TAB package in which when a memory chip is mounted in a tape automated bonding (TAB) type package according to a lead on chip method based upon a film carrier, no deterioration in the strength of bonding caused by the dislocation of bonding occurs, further forming of a metallic mold and others are not required and the cost is low, there is Japanese Patent Application Laid-Open No. Hei 6-13428. In the above bonding method, after an inner lead is bend and transformed by a bonding tool before bonding, the inner lead is pressurized by the bonding tool and bonded to an electrode pad of a chip.
SUMMARY OF THE INVENTION
However, it is clarified by the inventor that in the above bonding method, there is a problem that the center line of an inner lead cannot be recognized by an image recognition device because an electrode pad is located right under an inner lead.
Also, it is clarified by the inventor that in the above bonding method, there is a problem that the looped form of each inner lead after bonding is different because an error occurs in an interval between an inner lead and an electrode pad successively bonded by a bonding tool when a chip mechanically connected to an insulating film is tilted.
Further, it is clarified by the inventor that in the above bonding method, there is a problem that as an inner lead horizontally extended is bent and transformed by a bonding tool, the inner lead is distorted, stress is left in the inner lead after inner lead bonding and as a result, when stress generated by difference in the coefficient of thermal expansion (hereinafter called thermal stress) operates in a temperature cycle acceleration test and others, a part in which stress is left of the inner lead is cracked.
An object of the present invention is to provide bonding technique in which the center line of an inner lead can be recognized independent of an electrode pad.
Another object of the present invention is to provide bonding technique in which a looped form after bonding can be stabilized.
Another object of the present invention is to provide bonding technique in which stress can be prevented from being left in an inner lead after inner lead bonding.
Another object of the present invention is to provide bonding technique in which manufacturing based upon a tape can be realized by securing alignment based upon a tape.
The above objects, other objects, and the new characteristics of the present invention will be clarified from the description in this specification and attached drawings.
The outline of typical ones of inventions disclosed in the present invention will be described below.
That is, a method of manufacturing a semiconductor integrated circuit in which a semiconductor chip is mechanically connected to a carrier on one main surface of which plural inner leads are laid via an insulating film and each electrode pad of the semiconductor chip is bonded to the above each inner lead is characterized in that when the above inner lead is bonded to the above electrode pad, the position of the inner lead is observed individually or collectively and the inner lead is transformed by a bonding tool and bonded to the electrode pad based upon the result of the observation.
As an inner lead is transformed by a bonding tool based upon the observation of the position of the inner lead according to the above means, the inner lead can be precisely bonded to an electrode pad.
For the outline of the other invention, in a method of manufacturing &mgr;BGA·IC in which to stabilize the form of a letter S of an inner lead after bonding, a chip is fixed to a tape carrier on one main surface of which plural inner leads are laid via an insulating film and each electrode pad of the chip is bonded to each inner lead, when an inner lead is bonded to an electrode pad, first, a chip is supplied in a fixed position for a bonding tool using a sprocket hole of a tape carrier. Next, the respective positions of the inner lead and the electrode are recognized using a feature lead and the electrode pad. Afterward, after the center line of the inner lead is recognized, the inner lead is touched to the chip by the bonding tool, pressed in the direction of the base and bent in the form of a letter S, the end of the inner lead is bonded to the electrode pad by thermocompression by the bonding tool.
The other outline of typical ones of inventions disclosed in the present invention will be described below.
1. A bonding method in which a semiconductor chip is mechanically connected to a carrier on one main surface of which a group of inner leads are laid via an insulating film and after each electrode pad of the above semiconductor chip is aligned with each inner lead, each inner lead is bonded to each electrode pad of the semiconductor chip by a bonding tool and which is characterized by being provided with an image capturing process for capturing an image of the above inner lead having the above electrode pad as a background, an inner lead recognizing measuring line setting process for setting at least one image scanning line including the above electrode pad and at least one image scanning line on each side of the above electrode pad as each inner lead recognizing measuring line out of image scanning lines respectively perpendicular to the inner lead in the above captured image, a luminance measuring process for measuring luminance at each point on each scanning line every the above each inner lead recognizing measuring line, a forming process for adding luminance on the above each inner lead recognizing measuring line every same point and forming an added luminance distribution waveform, and a judging process for setting a threshold value for the above added luminance distribution waveform, calculating the center of gravity in an area equal to or larger than the threshold value and judging the center line of the above inner lead.
2. A bonding method in which a semiconductor chip is mechanically connected to a carrier on one main surface of which a group of inner leads are laid via an insulating film and after each electrode pad of the above semiconductor chip is aligned with each inner lead, each inner lead is bonded to each electrode pad of the semiconductor chip by a bonding tool and which is characterized by being provided with an image capturing process for capturing an image of the above inner lead having the above electrode pad as a background, an inner lead recognizing measuring line setting process for setting at least one
Katayama Yoshifumi
Nadamoto Keisuke
Ohkubo Tatsuyuki
Mattingly Stanger & Malur, P.C.
Nguyen Donghai
Vo Peter
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