Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2002-06-24

2003-12-09

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S049130, C365S051000, C365S200000, C365S230030

Reexamination Certificate

active

06661692

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit used as a semiconductor memory device or the like having a redundancy relief function for substituting a normal memory cell for a malfunctioning memory cell.
2. Description of the Related Art
A conventionally-known semiconductor integrated circuit includes a plurality of adjacent output circuit blocks having the same circuit layouts, i.e., shapes and areas of the output circuit blocks, positions of signal terminals thereof, etc., are the same, and a plurality of adjacent input circuit blocks having the same circuit layouts. In the conventionally-known semiconductor integrated circuit, an output signal provided from each output circuit block is input to a corresponding one of the input circuit blocks.
Further, in the case of connecting the input circuit blocks and the output circuit blocks using conductor lines, when a pitch between adjacent output circuit blocks is identical to that between corresponding adjacent input circuit blocks, the input and output circuit blocks can be connected using straight conductor lines such that a distance between the input circuit blocks and their corresponding output circuit blocks is the shortest possible, and therefore there are no unnecessary areas in the circuit layout. On the contrary, when the pitch between the adjacent output circuit blocks is not identical to the pitch between the adjacent input circuit blocks, the conductor lines for connecting the input and output circuit blocks are required to be bent so as not cross one another avoiding a short circuit, thereby increasing an area of a conductor region in which the conductor lines are provided.
One example of such a semiconductor integrated circuit having input and output circuit blocks is a flash memory which is a nonvolatile semiconductor memory. In general, the flash memory includes spare flash memory cells. When there is a malfunction in a main memory cell, the spare flash memory cell is substituted for the malfunctioning main memory cell (malfunctioning memory cell) such that data read/write operations or the like can be performed on the spare flash memory cell. By providing the spare flash memory cells, it is possible to suppress the occurrence of defects, thereby improving the yield of the flash memories. The flash memory usually uses a redundant circuit so as to substitute the spare flash memory cell for the malfunctioning memory cell. The redundant circuit includes a memory circuit for storing address information of the malfunctioning memory cell when the malfunctioning memory cell is present and a redundancy relief comparison circuit for comparing the address information of the malfunctioning memory cell and address information externally input to the redundant circuit.
In a DRAM, SRAM or the like, which are volatile semiconductor memories, a plurality of fuses made of polysilicon, metal or the like are provided. In order to store the address information of the malfunctioning memory cell, the plurality of fuses are electrically disconnected, for example. On the contrary, in the flash memory which is a nonvolatile semiconductor memory, for example, memory cells, which are nonvolatile semiconductor memory elements, are used instead of using fuses so as to store address information of a malfunctioning memory cell on which redundancy relief is performed and other information specific to the flash memory. The memory circuit using the memory cells which are the nonvolatile semiconductor memory elements is referred to as a CAM (contents addressable memory) circuit.
As shown in
FIG. 2
, a CAM circuit usually includes two floating gate-type transistors
2
and
3
, four N-type transistors
4
,
5
,
6
and
7
, and two P-type transistors
8
and
9
.
The P-type transistor
8
, the N-type transistor
4
and the floating gate-type transistor
2
are serially connected together in this order. A power supply voltage VCC is applied to a source of the P-type transistor
8
. The floating gate-type transistor
2
is connected to a drain of the P-type transistor
8
via the N-type transistor
4
. A ground potential Vss is applied to a source of the floating gate-type transistor
2
. Similarly, the P-type transistor
9
, the N-type transistor
5
and the floating gate-type transistor
3
are serially connected together in this order. The power supply voltage VCC is applied to a source of the P-type transistor
9
. The floating gate-type transistor
3
is connected to a drain of the P-type transistor
9
via the N-type transistor
5
. The ground potential Vss is applied to a source of the floating gate-type transistor
3
.
An output Vgate is provided by a bias voltage generation circuit
10
to a gate of each of the floating gate-type transistors
2
and
3
. An output VB is provided by a bias voltage generation circuit
11
to a gate of each of the N-type transistors
4
and
5
. A gate of the P-type transistor
8
is connected to a node N
4
to which the P-type transistor
9
and the N-type transistor
5
are connected. Agate of the P-type transistor
9
is connected to anode N
3
to which the P-type transistor
8
and the N-type transistor
4
are connected. A program voltage Vprg is applied by a voltage supply circuit (not shown) to a drain of each of the N-type transistors
6
and
7
. Program signals PRG
1
and PRG
2
are applied by their respective control circuits (not shown) to gates of the N-type transistors
6
and
7
, respectively. A source of the N-type transistor
6
is connected to a node N
1
to which the floating gate-type transistor
2
and the N-type transistor
4
are connected. A source of the N-type transistor
7
is connected to a node N
2
to which the floating gate-type transistor
3
and the N-type transistor
5
are connected.
The CAM circuit configured as described above can store only one bit of address information of the malfunctioning memory cell on which redundancy relief is performed. A plurality of CAM circuits together store the entire address information of the malfunctioning memory cell. When the CAM circuit stores one bit of the address information of the malfunctioning memory cell, an output terminal OUT
1
of the CAM circuit is connected to a redundancy relief address comparison circuit (not shown). Outputs from the plurality of CAM circuits which together store the address information of the malfunctioning memory cell are compared to an externally-input address by the redundancy relief comparison circuit. When the comparison results in a mismatch, access to a memory cell corresponding to the externally-input address is performed. When the comparison results in a match, access to the spare memory cell is performed. Also, it is possible to store information specific to the memory device, such as a device code, in the CAM circuit. In this case, the output terminal OUT
1
of the CAM circuit is connected to a buffer circuit or the like.
Since the CAM circuit includes two flash memory cells each being similar to the main memory cell, a circuit layout with respect to a position in which the CAM circuit is provided, a pitch between the CAM circuits, etc., is considerably restricted by a layout of the main memory cells.
FIG. 3
is a diagram for explaining that the position of the CAM circuit is restricted by the layout of the main memory cells. In
FIG. 3
, the flash memory includes in a main memory region
21
a plurality of floating gate-type transistors
20
which are the flash memories constituting the main memory and are provided in a matrix form. Each control gate of the plurality of floating gate-type transistors (flash memory cells)
20
provided in one direction is connected to word lines
22
or
26
(i.e., the word lines
22
are provided in odd columns and word lines
26
are provided in even columns). The word lines
22
and
26
are connected to a word line voltage control circuit
23
. When the word line voltage control circuit
23
controls an operation so as to

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