Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2002-02-06

2003-04-15

Nelms, David (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S296000, C257S306000, C365S016000

Reexamination Certificate

active

06548903

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a wiring structure of data lines in a semiconductor integrated circuit.
2. Description of the Related Art
Conventionally, a semiconductor integrated circuit, such as a DRAM, includes shield wires each interposed between data lines so as to avoid coupling noise from their adjacent wires. However, when the number of data bits is large, the required number of data lines becomes large, and hence the number of the shield wires accordingly increases. As a result, the wiring region of the data lines is disadvantageously enlarged. Japanese Unexamined Patent Application Publication No. 2001-23374 discloses a technique that in a DRAM, the write and read data lines which are not simultaneously used for transferring data are alternately wired and that the write data lines are utilized as shield wires during the read operation, while the read data lines are utilized as shield wires during the write operation. This wiring structure requiring substantially no shield wires prevents an increase in the wiring area.
FIG. 1
shows a wiring structure of data lines for transferring data between memory cell arrays and a data input/output circuit in a semiconductor integrated circuit as described above. Between the memory cell arrays and the data input/output circuit, there are alternately wired write data lines WDL and /WDL for transferring complementary write data during the write operation and read data lines RDL and /RDL for transferring complementary read data during the read operation. These write and read data lines WDL, /WDL, RDL and /RDL are wired by use of the same wire pitch as, for example, complementary bit lines BL and /BL (bit line pairs) (not shown). That is, the write data lines WDL and /WDL and the read data lines RDL and /RDL are wired corresponding to the respective bit line pairs in the memory cell arrays and are shared between these bit line pairs.
As shown in
FIG. 1
, there exist parasitic capacitances C
0
between the adjacent data lines. There also exist parasitic capacitances C
1
and C
2
between the data lines and the semiconductor substrate and between the data lines and a metal wire UL of the overlying layer, respectively. Since every data line has a total parasitic capacitance of “2C
0
+C
1
+C
2
”, the data transfer times (delay times) necessary for transferring the data along the respective data lines are equal.
In a semiconductor integrated circuit such as a system LSI including a DRAM core, data read from the DRAM core may be directly outputted to a controller in the integrated circuit, and data to be written into the DRAM core may be directly inputted from the controller. In the above semiconductor integrated circuit, simultaneously outputting to the controller many pieces of data read from the memory cells onto the bit lines and then amplified by the sense amplifiers can improve the data transfer rate. In this case, since the data lines cannot be shared between bit line pairs, the data lines must be formed corresponding to each bit line pair. For this reason, unlike
FIG. 1
, a plurality of wiring layers must be used to form the data lines.
FIG. 2
shows an example wherein two wiring layers L
1
and L
2
are used to wire the data lines. In this example, the write and read data lines WDL and /RDL are alternately wired in the wiring layer L
1
overlying the semiconductor substrate, and the read and write data lines RDL and /WDL are alternately wired in the wiring layer L
2
overlying the wiring layer L
1
. Using these two wiring layers L
1
and L
2
allows the write data lines WDL and /WDL and the read data lines RDL and /RDL to be wired corresponding to each bit line pair. For this reason, many pieces of data amplified by the sense amplifiers can be simultaneously outputted to the controller or the like via the write and read data lines WDL, /WDL, RDL and /RDL. This can improve the. data transfer rate.
In the wiring structure of
FIG. 2
, however, parasitic capacitances C
0
and C
3
exist between the adjacent data lines in the wiring layer L
1
and between the adjacent data lines in the wiring layer L
2
, respectively. Parasitic capacitances C
1
and C
2
also exist between the data lines of the wiring layer L
1
and the substrate and between the data lines of the wiring layer L
1
and the data lines of the wiring layer L
2
, respectively. Parasitic capacitances C
4
also exist between the data lines of the wiring layer L
2
and the metal wire UL of the overlying layer. As a result, in
FIG. 2
, every data line of the wiring layer L
1
has a total parasitic capacitance of “2C
0
+C
1
+C
2
”, while every data line of the wiring layer L
2
has a total parasitic capacitance of “2C
3
+C
2
+C
4
”.
In the wiring structure of
FIG. 2
, since the parasitic capacitances associated with the data lines are different between the wiring layers L
1
and L
2
, the data transfer times (delay times) necessary for transferring the data along the data lines of the wiring layers L
1
and L
2
are also different. In many cases, the insulator film formed on the semiconductor substrate is different in material and thickness from the insulator film formed under the metal wire UL. For this reason, the difference especially between the capacitances C
1
and C
4
is large. The parasitic capacitance difference results not only from the materials of the insulator films but also from the tolerance of the fabrication process.
Thus, there is a possibility that complementary write data transferred along the data lines WDL and /WDL cannot be transferred to the memory cell array at the same timing, resulting in an erroneous data write into the memory cells. Similarly, there is also a possibility that complementary read data transferred along the data lines RDL and /RDL cannot be transferred to the controller or the like at the same timing, resulting in incorrectly reading the data read from the memory cells.
SUMMARY OF THE INVENTION
It is an object of the present invention to prevent the circuit malfunction which would otherwise occur due to a parasitic capacitance difference, by equalizing the parasitic capacitances associated with the data lines in a semiconductor integrated circuit that uses a plurality of wiring layers to transfer data. In particular, it is an object of the present invention to prevent the circuit malfunction by equalizing the data transfer times when complementary data lines are used to transfer data.
According to one of the aspects of the semiconductor integrated circuit of the present invention, in the first region, a first data line is wired by use of a first wiring layer formed over a semiconductor substrate, and a second data line extending over the first data line is wired by use of a second wiring layer formed over the first wiring layer. In the second region, the second data line is wired by use of the first wiring layer, and the first data line extending over the second data line is wired by use of the second wiring layer. Here, data is transferred to the first and second data lines at respective different timings.
A switching region is formed between the first and second regions. In the switching region, the first data line wired in the first region is connected to the first data line wired in the second region, and the second data line wired in the first region is connected to the second data line wired in the second region. In the switching region, at least either of the first data lines and the second data lines are connected to each other via a third wiring layer formed over the semiconductor substrate.
In general, the parasitic capacitances formed between the data lines formed in the first wiring layer and the semiconductor substrate are different from the parasitic capacitances formed between the data lines formed in the second-wiring layer and its overlying wire. According to the present invention, vertically reversing positioning of the first and second data lines between the first and second regions substantially equalizes the total parasitic capacita

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