Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-01-07
2003-05-20
Tran, M. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233500
Reexamination Certificate
active
06567339
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which operates an internal circuit according to an external command supplied from the exterior of the semiconductor integrated circuit and an internal command generated in its interior, and more particularly, to a semiconductor integrated circuit including volatile memory cells.
2. Description of the Related Art
The semiconductor integrated circuit such as DRAM holds data in capacitors formed in the memory cells. Since the data written in the memory cells is gradually lost, refresh operation for rewriting the data at predetermined intervals is necessary. There has been recently proposed DRAM which internally generates a refresh request not only during a standby period but also during an operating period and automatically performs the refresh operation according to the request.
FIG. 1
shows the operation of the DRAM like the above. The DRAM receives the external command for performing read operation RD or write operation WR, thereby operating the internal circuit (memory array). In order to prevent a malfunction of the internal circuit, reception of the internal command (refresh command) is inhibited from the supply of the external command to the completion of the operation RD or WR of the internal circuit (inhibition period). The DRAM generates the internal command during a permission period except for the inhibition period, to perform refresh operation REF (FIG.
1
(
a
)). Namely, the DRAM is automatically able to perform the refresh operation when the read operation RD and the write operation WR of the memory array
22
are not performed. As a result of this, it is not necessary for a system, to which the DRAM is mounted, to generate the refresh request during the operating period as well as the standby period of the DRAM.
However, the inhibition period of the internal command is set after the received external command is decided to be correct. Hence, there occurs a deviation T
1
of a few ns from the reception of the external command until the inhibition of reception of the internal command. In the case where the refresh command is generated during the period T
1
(FIG.
1
(
b
)), the external command conflicts with the internal command, which results in the malfunction (duplicate operation) of the memory array
22
. As a result of this, the data held in the memory cells is destroyed.
The aforesaid disadvantage is caused in a semiconductor integrated circuit of a clock synchronous type such as SDRAM, not only in the DRAM operating asynchronously to the clock. Further, the aforesaid disadvantage is not a phenomenon which occurs only in the semiconductor memory. For example, in the case where an internal circuit of a logic LSI such as CPU operates according to a control command from the exterior and the internal circuit operates according to an interruption command which is generated in its interior, the CPU malfunctions when the control command conflicts with the interruption command.
SUMMARY OF THE INVENTION
It is an object of the present invention to prevent conflict of an external command supplied from the exterior and an internal command internally generated, and to prevent a malfunction of an internal circuit of a semiconductor integrated circuit.
More particularly, it is the object of the present invention to perform refresh operation with reliability in the semiconductor integrated circuit having volatile memory cells.
According to one of the aspects of the semiconductor integrated circuit of the present invention, an external command receiving circuit receives an external command signal supplied from the exterior of the semiconductor integrated circuit, in synchronization with one transition edge of a first clock signal supplied from the exterior. An internal command receiving circuit receives an internal command signal internally generated, in synchronization with the other transition edge of the first clock signal. Namely, receiving operation of the internal command signal by the internal command receiving circuit shifts from receiving operation of the external command signal by the external command receiving circuit by at least a half cycle of the first clock signal. This prevents the conflict in operation between the internal circuit according to the external command signal and the internal circuit according to the internal command signal even when the internal command signal is generated asynchronously to the first clock signal. Namely, it is possible to prevent the malfunction of the internal circuit.
A control circuit does not receive an operation request according to the internal command signal, immediately after starting the operation according to the external command signal. Hence, an operation margin of the control circuit improves, and the control circuit can operate the internal circuit without malfunction according to the external command signal received in the external command receiving circuit or the internal command signal received in the internal command receiving circuit.
According to another aspect of the semiconductor integrated circuit of the present invention, the external command receiving circuit receives the external command signal in synchronization with a rising edge of the first clock signal, and the internal command receiving circuit receives the internal command signal in synchronization with a falling edge of the first clock signal. In the semiconductor integrated circuit, in general, the external command signal is received in synchronization with a rising edge of the clock signal (the first clock signal). Therefore, it is possible to design a receiving circuit of the external command signal in the logic of the conventional art, and to improve its design efficiency.
According to another aspect of the semiconductor integrated circuit of the present invention, the internal command receiving circuit has a phase inverting circuit for inverting the phase of the first clock signal to generate a second clock signal. The internal command signal is received in synchronization with a rising edge of the second clock signal. Therefore, only formation of a simple phase inverting circuit makes it possible to shift receiving timing of the internal command signal from receiving timing of the external command signal (the rising edge of the first clock signal) by a predetermined time.
According to another aspect of the semiconductor integrated circuit of the present invention, the external command receiving circuit receives the external command signal supplied from the exterior of the semiconductor integrated circuit, in synchronization with the first clock signal supplied from the exterior. A clock generator converts the first clock signal to the second clock signal whose phase is different from that of the first clock signal. The internal command receiving circuit receives the internal command signal internally generated, in synchronization with the second clock signal. Namely, the receiving operation of the external command signal by the external command receiving circuit shifts from the receiving operation of the internal command receiving circuit by the internal command receiving circuit by a phase difference between the first clock signal and the second clock signal. This can prevent the conflict in operation between the internal circuit according to the external command signal and the internal circuit according to the internal command signal.
The control circuit does not receive the operation request according to the internal command signal immediately after starting the operation according to the external command signal. Hence, the operation margin of the control circuit improves, and the control circuit can operate the internal circuit without malfunction according to the external command signal received in the external command receiving circuit or the internal command signal received in the internal command receiving circuit.
According to another aspect of the semiconductor integrated circuit of the present invention, the
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Tran M.
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