Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-11-07

2003-05-06

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S203000

Reexamination Certificate

active

06559700

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit capable of operating at a high speed at a low voltage, and in particular to a semiconductor integrated circuit using a pass transistor logic circuit including a combination of FET pass transistor gates.
2. Description of the Related Art
A conventional pass transistor logic circuit is disclosed in Low-Voltage/Low-Power Integrated Circuits and Systems, IEEE PRESS, pp. 202-204 and Japanese Laid-Open Publication No. 10-135814.
FIG. 16
shows an example of a conventional pass transistor logic circuit. The pass transistor logic circuit shown in
FIG. 16
includes a buffer circuit
59
and a pass transistor network
60
. The pass transistor network
60
is connected to the buffer circuit
59
through a connection line
50
a.
The buffer circuit
59
includes a CMOS inverter
59
a
including a P-type MOSFET
59
b
and an N-type MOSFET
59
c,
and a pull-up P-type MOSFET
59
d.
A source of the P-type MOSFET
59
b
is connected to a power supply line
50
, and a drain and a gate of the P-type MOSFET
59
b
are respectively connected to a drain and a gate of the N-type MOSFET
59
c.
A source of the N-type MOSFET
59
a
is connected to a GND line
51
(i.e., grounded). The gate of the P-type MOSFET
59
b
and the drain of the N-type MOSFET
59
c
act as an input terminal
50
c,
and the drain of the P-type MOSFET
59
b
and the gate of the N-type MOSFET
59
c
act as an output terminal
58
. A source of the P-type MOSFET
59
d
is connected to the power supply line
50
, and a gate and a drain of the P-type MOSFET
59
d
are respectively connected to the output terminal
58
and the input terminal
50
c.
The pass transistor network
60
includes four N-type MOSFETs
52
,
53
,
56
and
57
which form a pass transistor tree. A drain of the N-type MOSFET
52
is connected to a drain of the N-type MOSFET
57
. A gate and a source of the N-type MOSFET
57
are respectively connected to a control input terminal
57
a
and an input terminal
55
b.
A gate of the N-type MOSFET
52
is connected to a control input terminal
52
a.
A source of the N-type MOSFET
52
is connected to a drain of the N-type MOSFET
53
and also to a drain of the N-type MOSFET
56
. Similarly, a gate and a source of the N-type MOSFET
53
are respectively connected to a control input terminal
53
a
and an input terminal
54
a.
A gate and a source of the N-type MOSFET
56
are respectively connected to a control input terminal
56
a
and an input terminal
55
b.
Signals which are input to an input terminal
54
a,
55
a
and
55
b
respectively connected to the sources of the three N-type MOSFETs
53
,
56
and
57
are processed with a prescribed logic operation based on a signal applied to the control input terminals
52
a,
53
a,
56
a
and
57
a.
The resultant signal is output to the input terminal
50
c
of the CMOS inverter
59
a
of the buffer circuit
59
through the connection line
50
a
from a connection point
50
b
between the drains of the two N-type MOSFETs
52
and
57
. The signal is amplified and waveform-shaped by the CMOS inverter
59
a
and output from the output terminal
58
of the CMOS inverter
59
a
to an external circuit.
The pass transistor network
60
shown in
FIG. 16
includes a two-stage pass transistor tree, but a more complicated logic circuit includes a pass transistor tree of more than two stages.
FIG. 17
shows an example of such a pass transistor network
80
.
FIG. 17
shows a pass transistor logic circuit including the pass transistor network
80
including six N-type MOSFETs
61
m
through
66
m
connected in series, and a buffer circuit
68
including a CMOS inverter and a pull-up P-type MOSFET, like the buffer circuit
59
. The six N-type MOSFETs
61
m
through
66
m
are connected in series through connection of a drain and a source of two adjacent MOSFETs. A drain of the sixth-stage N-type MOSFET
66
m
is connected to an input terminal of the buffer circuit
68
(i.e., an input terminal of the CMOS inverter). The pass transistor network
80
includes control input terminals
61
through
66
and an input terminal
67
. The control input terminals
61
through
66
are respectively connected to gate terminals of the N-type MOSFETs
61
m
through
66
m
. The input terminal
67
is connected to a source of the N-type MOSFET
61
m.
A signal which is input to the input terminal
67
is processed with a prescribed logic operation based on signals applied to the control input terminals
61
through
66
. The resultant signal is output from the drain of the N-type MOSFET
66
m
to the input terminal of the CMOS inverter of the buffer circuit
68
. The signal is amplified and waveform-shaped by the CMOS inverter and output from an output terminal
69
of the buffer circuit
68
, the output terminal
69
being connected to an output terminal of the CMOS inverter.
FIG. 18
is a graph illustrating a delay characteristic of an input/output voltage of the pass transistor logic circuit shown in FIG.
17
. The horizontal axis represents time, and the vertical axis represents the input/output voltage. An input voltage In-
68
shown in
FIG. 18
represents a voltage of a signal which is input to the input terminal
67
of the pass transistor network
80
. The input voltage In-
68
, which periodically changes from a LOW level to a HIGH level, passes through the N-type MOSFETs
61
m
through
66
m
connected in series and then is input to the input terminal of the buffer circuit
68
. The signal is then output to the output terminal
69
of the buffer circuit
68
. An output voltage Out-
68
represents a voltage of the signal which is output to the output terminal
69
. The input voltage In-
68
increases from the ground level GND to the supply voltage level Vdd over-time. The output voltage Out-
68
is obtained by inversion performed by the CMOS inverter, and thus decreases from the supply voltage level Vdd to a level representing an OFF state.
As described above, the pass transistor network
80
includes six N-type MOSFETs
61
m
through
66
m
. Therefore, when the input voltage of the buffer circuit
68
changes from the LOW level to the HIGH level, the voltage level does not rise to the supply voltage level Vdd but rises only to a voltage level which is lower than the supply voltage level Vdd by a threshold voltage of the N-type MOSFETs. The input voltage In-
68
increases over-time, and the drain-source voltage and the gate-source voltage of each of the N-type MOSFETs
61
m
through
66
m
decrease. Therefore, the amplification degree of each of the Ntype MOSFETs
61
m
through
66
m
approaches an OFF region (saturation region), and the gradient of rise of the input voltage of the buffer circuit
68
from the LOW level to the HIGH level is slower. When the input voltage In-
68
becomes Vi at time t
0
, the output voltage Out-
68
at the output terminal
69
decreases from the supply voltage level Vdd by a threshold voltage of the P-MOSFET to a level Vo. Therefore, the P-MOSFET is turned ON, and the input voltage In-
68
is raised to the supply voltage level Vdd (i.e., pulled up). The pulled-up voltage In-
68
is input to the buffer circuit
68
, and a signal having the output voltage Out-
68
is output from the output terminal
69
of the buffer circuit
68
.
Since a signal which is input to the input terminal
67
passes through the six N-type MOSFETs
61
m
through
66
m
connected in series, the signal rises from a LOW level to a HIGH level very slowly and thus the propagation time of the signal is increased. In the buffer circuit
68
having a CMOS inverter, when the rise of the input signal from a LOW level to a HIGH level is slow, a significant delay is caused in the signal propagation time before the input voltage In-
68
reaches the signal inversion level (threshold level). In addition, since the transition time before the input voltage In-
68
reaches the signal inversion level is excessively long, a large shoot-through current flows, resulting in an

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