Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-11-27
2002-10-29
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230060, C365S189050
Reexamination Certificate
active
06473359
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and more specifically it relates to a semiconductor integrated circuit that performs digital/analog D/A conversion.
Current cell circuits that achieve output currents that are equal or exponentials of 2, are employed in a digital/analog converter (hereafter referred to as a D/A converter) and the like. An example of a D/A converter employing equal current cell circuits in the prior art is explained below with reference to FIG.
7
.
As illustrated in
FIG. 7
, a D/A converter
400
comprises equal current cell circuits
450
arrayed in a matrix, a row decoder
410
and a first latch circuit
430
that make selections in the direction of the rows of the matrix of the equal current cell circuits
450
, a column decoder
420
and a second latch circuit
440
that make selections in the direction of the columns of the matrix of the equal current cell circuits
450
.
As shown in
FIG. 7
, the three high order bits of an input A (
5
:
0
), i.e., A
5
, A
4
and A
3
, are input to the row decoder
410
, and seven-bit data (the individual bits are indicated with reference numbers D
0
-D
6
) are output to the first latch circuit
430
. In the row decoder
410
, specific logic elements are provided in correspondence to the individual sets of data D
0
-D
6
so that the truth table illustrated in
FIG. 9
is achieved. In addition, the three low order bits of the input A (
5
:
0
), i.e., A
2
, A
1
and A
0
are input to the column decoder
420
, and seven-bit data are output to the second latch circuit
440
in a similar manner.
Now, the structure of the row decoder
410
and its relationship with its output, i.e. , the individual sets of data D
0
-D
6
, are explained. Since the structure of the column decoder
420
is essentially identical to that of the row decoder
410
, its explanation is omitted.
The data D
0
are the output of a three-input NAND element NAND
0
into which inverted signals of A
5
, A
4
and A
3
are input. The data D
1
are the output of a two-input NAND element NAND
1
into which inverted signals of A
5
and A
4
are input. The data D
2
are the output of a two-input NAND element NAND
2
into which the output of a two-input OR element OR
2
into which inverted signals of A
4
and A
3
are input and an inverted signal of A
5
are input. The data D
3
are the output of an inverter element INV
5
into which an inverted signal of A
5
is input. The data D
4
are the output of a two-input NOR element NOR
4
into which the output of a two-input AND element AND
4
into which inverted signals of A
4
an A
3
are input and an inverted signal of A
5
are input. The data D
5
are the output of a two-input NOR element NOR
5
into which inverted signals of A
5
and A
4
are input. The data D
6
are the output of a three-input NOR element NOR
6
into which inverted signals of A
5
, A
4
and A
3
are input. The row decoder
410
structured as described above achieves the truth Table shown in FIG.
9
.
The first latch circuit
430
latches the output of the row decoder
410
in synchronization with a clock CLK. The output of the first latch circuit
430
is input to the equal current cells
450
, to be detailed later, as inputs i and i+1. Likewise, the second latch circuit
440
latches the output from the column decoder
420
in synchronization with the clock CLK. The output of the second latch circuit
440
is input to the equal current cells
450
, to be detailed later, as an input j.
The equal current cells
450
, which are provided in an 8×8 matrix as illustrated in
FIG. 7
, are connected to the first latch circuit
430
and the second latch circuit
440
. The inputs i and i+1 connected to the first latch circuit
430
and the input j connected to the second latch circuit
440
are input to the equal current cells
450
.
An output Qm (m represents an integer equal to or greater than 0 and equal to or less than 6) of the first latch circuit
430
is input to the individual equal current cells in row m+2 as the input i and also is input to the individual equal current cells in row m+l as the input i +1. The input i in the first row that is not connected to the first latch circuit
430
is instead connected to a source Vdd, and likewise, the input i+1 in the eighth row that is not connected to the first latch circuit
430
is instead connected to the ground GND.
An output Qn (n represents an integer equal to or greater than 0 and equal to or less than 6) of the second latch circuit
440
is input to the individual equal current cells in row n as the input j. The input j in the seventh row that is not connected to the second latch circuit
440
is instead connected to the ground GND.
Now, the circuit structure of the equal current cells
450
is explained in reference to FIG.
8
. The input i is input to one input of a NAND element
452
via inverter elements
456
and
457
. The output of the inverter element
456
is connected to the gate terminal of an NMOS capacitor N
1
. The input i+1 and the input j are input to a two-input OR element
451
. The output of the two-input OR element
451
is input to another input of the NAND element
452
. The output of the NAND element
452
is connected to the gate terminal of an NMOS capacitor N
2
and is also input to a current switch portion
459
which is to be detailed later.
Next, the structure of the current switch portion
459
in each equal current cell
450
is explained. A PMOS Q
3
, which is set in a drain saturation region by a bias voltage, functions as a constant current source. PMOS's Q
1
and Q
2
constituting the current switch portion
459
are turned ON/OFF by a selection signal SEL which is an output from the two-input NAND element
452
. The selection signal SEL is connected to the gate terminal of the PMOS Q
1
via an inverter element
455
and an inverter element
454
, and is also connected to the gate terminal of the PMOS Q
2
via the inverter element
455
.
When the selection signal SEL is 0, the PMOS Q
1
is set to ON and the PMOS Q
2
is set to OFF, whereas when the selection signal SEL is at 1, the PMOS Q
1
is set to OFF and the PMOS Q
2
is set to ON. In addition, when the selection signal SEL shifts either from 0 to 1 or from 1 to 0, the PMOS's Q
1
and Q
2
are set to OFF or ON together. When the PMOS's Q
1
and Q
2
are set to ON or OFF together, the drain voltage at the PMOS Q
3
fluctuates to result in a fluctuation in the current in the output out due to charging/discharging of the incidental capacitance Cp to generate noise, which, in turn, affects the length of time required for settling.
When the PMOS Q
1
is set to ON, the source Vdd is output as the output out via the PMOS Q
1
. When the PMOS Q
2
is set to ON, on the other hand, the source Vdd is output as an output out b via the PMOS Q
2
. Both the outputs out and out b are wired throughout the matrix.
As an example, the operation of the equal current cells
450
that is performed when “011010” is input to the input A (
5
:
0
). The input A (
5
:
0
) is divided into 3-bit groups to be respectively input to the row decoder
410
and the column decoder
420
. The row decoder
410
and the column decoder
420
have the same logic and achieve the truth table shown in FIG.
9
. When “011” representing the high order three bits of the input is input to the row decoder
410
, it outputs “1110000” as indicated in the truth table in FIG.
9
. Likewise, when “010” representing the low order bits of the input is input to the column decoder
420
, it outputs “1100000” as indicated in the truth table in FIG.
9
.
The first latch circuit
430
and the second latch circuit
440
output their inputs in synchronization with the clock CLK. In the first row in the matrix of the equal current cells
450
, since the inputs i and i+1 of the equal current cells
450
are at high level, the current is switched toward the out. The same applies to the second row and the third row.
Since the i input is at high level and
Hoang Huan
Oki Electric Industry Co, Ltd.
Rabin & Berdo P.C.
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