Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-09-06

2002-12-10

Phan, Trong (Department: 2818)

Static information storage and retrieval

Powering

C365S189090, C365S203000

Reexamination Certificate

active

06493282

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit with a dynamic random-access memory (DRAM).
Recently, an LSI, in which a logic circuit, like a central processing unit (CPU) or application-specific integrated circuit (ASIC), and a DRAM have been integrated together on a single semiconductor substrate, has been the object of much attention. In the following description, a semiconductor integrated circuit of this type will be referred to as a “DRAM-built-in LSI”, which is also called an “LSI with an embedded DRAM”. A DRAM-built-in LSI is attractive, because an LSI of this type realizes various functions, which have had to be executed using multiple chips including logic and general-purpose DRAM chips, by a single chip.
For a DRAM-built-in LSI, there is no need to interconnect multiple chips together by way of long wires. In addition, the same bonding pad can be used for both the logic and memory circuits alike. Accordingly, the LSI occupies a smaller area when mounted on a circuit board. Furthermore, the shorter wire length contributes to decreasing the wiring capacitance and increasing the data transfer rate. Moreover, no drivers of a great size are needed anymore because those long wires can be eliminated. As a result, the power dissipation of the overall system can be reduced advantageously.
Hereinafter, a typical known DRAM-built-in LSI, including a stacked capacitor DRAM, will be described. In the LSI of this type, its logic circuit is implemented as a complementary metal-oxide semiconductor (CMOS) circuit.
FIG. 8
is a cross-sectional view schematically illustrating a structure for a known DRAM-built-in LSI including a stacked capacitor DRAM. The LSI shown in
FIG. 8
includes p-type semiconductor substrate (p-SUB)
91
, n-wells (NWs)
92
and
94
, p-well (PW)
93
, n-channel MOS (NMOS) memory access transistor
95
, stacked memory cell capacitor
96
and NMOS and p-channel MOS (PMOS) transistors
97
and
98
for a logic circuit.
As shown in
FIG. 8
, the NWs
92
and
94
and the PW
93
have been defined in the p-SUB
91
. Multiple n
+
- and p
+
-type doped regions have also been defined in the p-SUB
91
. The NMOS memory access transistor
95
is connected to a data line BL and a word line WL. A supply voltage VDD is applied to the NWS
92
and
94
, while a substrate bias voltage VBB, lower than the ground voltage, is applied to the PW
93
.
In a DRAM-built-in LSI in general, the transistors and capacitors thereof are downsized to increase the operating speed of its logic circuit, and the transistors are integrated together highly densely in its DRAM to reduce the necessary chip area. As shown in
FIG. 8
, an NMOS transistor is used as the memory access transistor
95
. On the other hand, the memory cell capacitor
96
has a three-dimensional structure (e.g., implemented as a stacked type) to produce a capacitance large enough to stabilize the operation of the DRAM. Furthermore, the PW
93
is included in the NW
92
that has been defined in the p-SUB
91
, thus forming a so-called “triple well structure”.
The PW
93
, NW
92
and p-SUB
91
are supplied with such voltages that will make their pn junctions reverse biased.
Specifically, the p-SUB
91
, NW
92
and PW
93
are biased to the ground voltage, the supply voltage VDD and a negative voltage VBB, which is lower than the ground voltage, respectively. The voltages VDD and VBB are output from a power supply circuit (not shown) formed on the p-SUB
91
.
By forming the memory access transistor
95
and memory cell capacitor
96
over the triple well structure and by biasing those wells to these levels, the memory and logic circuits can be electrically isolated from each other. In addition, the threshold voltage of the memory access transistor
95
is set high enough so that the charges stored on the memory cell capacitor
96
do not leak into the data line BL by way of the memory access transistor
95
.
The voltage on the data line BL will be somewhere between the ground voltage and the supply voltage VDD. To read or write data from/on the memory cell capacitor
96
, a voltage higher than the supply voltage VDD by the threshold voltage of the memory access transistor
95
should be applied to the gate electrode of the transistor
95
. Accordingly, either a voltage generated by an internal booster or an externally in-put voltage should be applied onto the word line WL.
In the logic circuit section on the other hand, the NMOS and PMOS transistors
97
and
98
, existing over the p-SUB
91
and NW
94
, respectively, form part of a CMOS logic circuit. In the CMOS logic circuit, the NMOS and PMOS transistors
97
and
98
operate mutually complementarily. Since the p-SUB
91
is biased to the ground voltage, the threshold voltage does not increase or the operating speed does not decrease.
A DRAM-built-in LSI of this type, however, requires a fabrication process much more complicated than a normal CMOS process. Also, a greater number of process steps or masks are needed, thus raising the fabrication costs disadvantageously. For example, the process steps of forming the triple well structure and forming the stacked memory cell capacitor should be carried out in addition to those of a normal CMOS process.
Moreover, where the stacked capacitor is formed over the data line, the upper electrode thereof should be located at a rather high level, thus increasing the aspect ratio of a via that connects the first- and second-level interconnects together. Accordingly, it is much more difficult to form such an interconnect structure. Furthermore, after the transistors have been formed for the CMOS logic circuit, a capacitive insulating film should be formed at an elevated temperature for the stacked capacitor. Thus, the transistors of the CMOS logic circuit might have their performance degraded.
Furthermore, a charge-pump-type voltage step-up power supply circuit should be provided to apply the voltage, higher than the supply voltage VDD, as a word line drive voltage. A charge-pump-type negative voltage power supply circuit should also be provided to bias the well, on which the memory cell will be formed, to the voltage lower than the ground voltage. These charge-pump-type power supply circuits, however, often cause a great, inconstant variation in the voltage supplied. This is a problem inevitable for the power supply circuits of this type due to their constructions. Accordingly, not so great a margin is allowable for the voltage or temperature range in which the DRAM can operate stably enough.
Considering the compatibility with the CMOS process, it would be more advantageous to integrate a static random-access memory (SRAM), not the DRAM, with the CMOS logic circuit on the same semiconductor substrate. However, a normal six-transistor SRAM cell is greater in area than a DRAM cell almost tenfold. Accordingly, the SRAM would require a much greater chip area. Consequently, even in compliance with the currently minimum possible design rule of 0.18 &mgr;m, for example, the SRAM built in the chip can have a storage capacity of just several hundreds kilobits at most.
In contrast, a DRAM cell is much smaller in area than an SRAM cell. Thus, a great number of DRAM cells can be integrated together on a single chip. That is to say, a CMOS logic circuit and a DRAM with a large storage capacity can be integrated together on a small-area chip. However, the known DRAM-built-in LSI requires a much higher process cost and likely results in performance degradation of the CMOS logic circuit thereof as described above. Accordingly, the effective applications of the known DRAM-built-in LSI are virtually limited to transferring an enormous quantity of data at a high speed by using a DRAM that has a rather great storage capacity and a bus of a broad enough bit width (e.g., graphics applications).
On the other hand, there are many applications requiring a memory with a storage capacity of about 1 to 4 megabits, which may be regarded as a “medium capacity” in accordance with the minimum design ru

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