Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-03-09

2002-08-13

Ho, Hoai V. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With pn junction isolation

C257S173000, C257S175000

Reexamination Certificate

active

06433407

ABSTRACT:

FIELD OF THE INVENTION
The present invention in general relates to a semiconductor integrated circuit device (hereafter, semiconductor integrated circuit). More particularly, this invention relates to a technology effectively applicable to an I/O circuit of a master slice semiconductor integrated circuit.
BACKGROUND OF THE INVENTION
In general, a semiconductor integrated circuit comprising a CMOS is provided with a protection circuit for protecting an I/O circuit from an electrostatic breakdown. When the protection circuit is composed of a CMOS transistor, there is a possibility that a MOS transistor of the protection circuit is broken down by a static electricity. For this reason, an element for protecting the MOS transistor of the protection circuit is further required.
FIG. 1
is a circuit diagram showing an I/O circuit including a conventional protection circuit. The I/O circuit is composed of a P-channel MOS transistor
11
, an N-channel MOS transistor
12
and an input buffer
13
. An output signal of an internal circuit
10
is supplied to a gate of the P-channel MOS transistor
11
and a gate of the N-channel MOS transistor
12
.
A drain of the P-channel MOS transistor
11
and a drain of the N-channel MOS transistor
12
are connected in common to a pad
19
via a signal line
18
. A first power supply voltage VDD and a second power supply voltage VSS (VSS<VDD) are applied to a source of the P-channel MOS transistor
11
and a source of the N-channel MOS transistor
12
, respectively. An input terminal and an output terminal of the input buffer
13
are connected to the pad
19
and the internal circuit
10
, respectively.
The following is a description on an operation of the I/O circuit having a configuration shown in FIG.
1
. For example, the first power supply voltage VDD is set as a reference voltage, and an excessive high voltage more than the first power supply voltage VDD is applied to the pad
19
by a static electricity or the like. In such a case, a parasitic diode (not shown) of the P-channel MOS transistor
11
and the P-channel MOS transistor
11
both become an on state. For this reason, the inputted excessive high voltage is limited by the first power supply voltage VDD, and then, is inputted to the internal circuit
10
.
On the other hand, for example, the second power supply voltage VSS is set as a reference voltage, and a negative excessive high voltage more than the VSS is applied to the pad
19
. In such a case, likewise, a parasitic diode (not shown) of the N-channel MOS transistor
12
and the N-channel MOS transistor
12
both become an on state. For this reason, a voltage applied to the internal circuit
10
becomes the second power supply voltage VSS.
As described above, the P-channel MOS transistor
11
and the N-channel MOS transistor
12
are operated as a protection circuit for preventing an excessive voltage more than the first power supply voltage VDD or a negative excessive voltage more than the second power supply voltage VSS from being applied to the internal circuit
10
.
Moreover, in the I/O circuit having the configuration shown in
FIG. 1
, a parasitic resistor (not shown) exists between the signal line
18
connected to the pad
19
and the drain of the P-channel MOS transistor
11
or the drain of the N-channel MOS transistor
12
. The parasitic resistor functions as a protection element for preventing an excessive level input voltage from being applied directly to the P-channel MOS transistor
11
and its parasitic diode when a positive excessive voltage more than the first power supply voltage VDD is applied to the pad
19
.
When there is no protection element as described above, an excessive level input voltage is applied directly to the P-channel MOS transistor
11
and its parasitic diode, and thereby, a leakage current flows there through; as a result, an IC is deteriorated. The similar disadvantage occurs in when a negative excessive voltage more than the second power supply voltage VSS is applied to the pad
19
. Namely, the parasitic resistor prevents an excessive level input voltage from being applied directly to the N-channel MOS transistor
12
and its parasitic diode.
However, in recent years, in order to rapidly achieve a downsizing or high driving performance of IC, a silicide process is employed, and thereby, a parasitic resistance of a source or drain of transistor is suppressed smaller. For this reason, the parasitic resistance is not enough to protect a gate oxide film of the P-channel MOS transistor
11
or N-channel MOS transistor
12
.
In a recent I/C circuit, as shown in
FIG. 2
, resistors
15
and
16
made of the same polysilicon as gate are interposed between the signal line
18
and the drain of the P-channel MOS transistor
11
or the drain of the N-channel MOS transistor
12
. These resistors
15
and
16
have about tens of ohm (&OHgr;).
However, in particular, when these resistors
15
and
16
having about tens of ohm are inserted in an I/O circuit having a high driving speed, an output level from the pad
19
changes due to a voltage drop by a current flowing through these resistors
15
and
16
. As a result, there is a problem that an output characteristic is deteriorated. For example, in the case of an output circuit, which has resistors
15
and
16
individually having a resistance value of 50 &OHgr; and flows a output current of 12 mA, a fluctuation of output level by its voltage drop becomes 1.2 V. For this reason, the I/O circuit having the aforesaid protection circuit has disadvantage characteristic in the case of driving another circuit connected thereto.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit, which can effectively prevent a breakdown of a protection transistor of a protection circuit for protecting a breakdown of a gate oxide film by a static electricity or the like, without changing the output circuit characteristics.
The semiconductor integrated circuit according to this invention has a construction as explained below. That is, in a master slice I/O circuit, a protection circuit with respect to an internal circuit is constructed in a manner that a protection element array is composed of a P-channel MOS transistor, a resistor and an N-channel MOS transistor, and a plurality of protection element arrays are arranged in a state of being connectable in parallel. Further, a proper number of protection element arrays are connected in parallel in accordance with a desired driving performance.
FIG. 3
is a circuit diagram that explains the principle of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit is a master slice I/O circuit, and has a circuit configuration such that a plurality of protection element arrays
2
,
2
, . . . are arranged between an internal circuit
20
and a pad
29
. In the I/O circuit, in order to obtain a desired driving performance, a wiring connection pattern is modified so that a proper number of protection element arrays
2
,
2
, . . . are connectable in parallel. In
FIG. 3
, there is shown a state that a proper number of protection element arrays
2
,
2
, . . . are connected in parallel. In
FIG. 3
, a reference numeral
23
denotes an input buffer.
Each protection element array
2
has the same configuration. The protection element array
2
includes a P-channel MOS transistor
21
, two resistors
25
and
26
and an N-channel MOS transistor
22
. A source of the P-channel MOS transistor
21
is connected to a first power supply voltage terminal supplying a first power supply voltage VDD. A gate of the P-channel MOS transistor
21
is connected to an output terminal of the internal circuit
20
. A drain of the P-channel MOS transistor
21
is connected to one terminal of the first resistor
25
.
The other terminal of the first resistor
25
is connected to a signal line
28
connected to the pad
29
and one terminal of the second resistor
26
. The other terminal of the second resistor
26
is connected to a drain of the

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