Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-07-14

2002-12-31

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C438S128000, C438S129000

Reexamination Certificate

active

06501108

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly it relates to the structure of a connecting portion for an insulated gate field effect transistor of a semiconductor integrated circuit.
2. Description of the Related Art
Semiconductor elements such as insulated gate field effect transistors (hereunder, MOSFETS) in semiconductor integrated circuits are miniaturized or highly densified in order to achieve higher integration and higher speed of semiconductor integrated circuits. Multilayer wiring is also employed to achieve higher densification of semiconductor integrated circuits.
The reduction of gate lengths occurring with miniaturization of MOSFETs has led to increased driving power for active elements, and accelerated speed for semiconductor integrated circuits. However, the parasitic capacitance is also increased, constituting a major hindrance to higher speeds of semiconductor integrated circuits. A well-known instance is increased parasitic capacitance occurring between wiring layers connecting a plurality of semiconductor elements, which results in reduced signal transmission speed and crosstalk between wiring layers (the phenomenon of signal noise between adjacent wiring layers) due to such parasitic capacitance. In the case of semiconductor elements such as MOSFETs with a microlevel structure, the increase in parasitic capacitance in the MOSFET is considerable.
The structure of a conventional MOSFET will now be explained with reference to the attached drawings.
FIG. 1
is a plan view of an inverter with a CMOS structure, and
FIG. 2
is a schematic view of a cross-section of FIG.
11
through line I-I.
As shown in
FIG. 1
, there are formed a P-channel MOSFET
101
serving as the inverter loader and an N-channel MOSFET
102
serving as the inverter driver. The P-channel MOSFET
101
comprises a gate electrode
103
, and a source diffusion layer
104
(
104
a
) and drain diffusion layer
105
sandwiching the gate electrode
103
. Here, the source diffusion layer
104
(
104
a
) is connected to a source electrode
107
through a plurality of source contact holes
106
, and the drain diffusion layer
105
is likewise connected to a drain electrode
109
through a plurality of drain contact holes
108
. Similarly, the N-channel MOSFET
102
comprises a gate electrode
103
, and a source diffusion layer
110
(
110
a
) and drain diffusion layer
111
sandwiching the gate electrode
103
. The source diffusion layer
110
(
110
a
) is connected to a source electrode
113
through source contact holes
112
, and the drain diffusion layer
111
is likewise connected to a drain electrode
115
through drain contact holes
114
.
The drain electrodes
109
and
115
of the P-channel MOSFET
101
and the N-channel MOSFET
102
are thus both connected to the wiring layer
116
via throughholes (not illustrated). Also, the source electrode
107
of the P-channel MOSFET
101
is connected to power source wiring (not illustrated) while the source electrode
113
of the N-channel MOSFET
102
is connected to GND wiring (not illustrated).
The cross-section will now be explained with reference to FIG.
2
. As shown in
FIG. 2
, the gate electrode
103
is formed on the surface of a semiconductor board
117
via source diffusion layers
104
and
104
a
and a gate insulating film
118
. The source diffusion layers
104
and
104
a
are each connected to the source electrode
107
through a source plug
119
, and the drain diffusion layer
105
is connected to the drain electrode
109
through a drain plug
120
. The drain electrode
109
is also connected to the wiring layer
116
through a throughhole plug
121
. Here, the source plug
119
and drain plug
120
are both composed of semiconductors filling the contact holes. Similarly, the throughhole plug is made by a semiconductor filling the throughhole.
When a MOSFET of this type of inverter is miniaturized, the distance X between the source electrode
107
and the drain electrode
109
and the distance Y between the gate electrode
103
and the drain plug
120
are both shortened.
According to the conventional technique described above, it is impossible to avoid the problem of parasitic capacitance mentioned above. This problem of parasitic capacitance will now be explained in detail with reference to FIG.
2
through FIG.
4
.
FIG. 3
shows the distance X between the source electrode
107
and the drain electrode
109
on the horizontal axis, and the parasitic capacitance value per unit length of the drain electrode
109
on the vertical axis. Here, the interlayer insulating film between the source electrode and drain electrode is a silicon oxide film. As clearly seen in
FIG. 3
, a smaller distance X results in a larger parasitic capacitance value. It is seen that when the distance X between the source electrode and drain electrode is below 1 &mgr;m, a particularly notable increase in the parasitic capacitance value occurs.
FIG. 4
shows the distance Y between the gate electrode
103
and the drain plug
120
(contact hole) on the horizontal axis and the parasitic capacitance value per unit length of the gate electrode on the vertical axis. As seen in
FIG. 4
, a smaller distance Y results in a larger parasitic capacitance value. In this case, the increase in the parasitic capacitance value is particularly notable when the distance Y is below 0.2 &mgr;m.
Thus, the increase in parasitic capacitance in a MOSFET region is considerable in the case of miniaturization of the MOSFET structure accompanying high integration or high speed modification of the semiconductor integrated circuit. This problem becomes more notable when the design dimensions of the semiconductor integrated circuit are reduced.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit in which the parasitic capacitance of the semiconductor element region can be easily reduced even when the semiconductor element of the semiconductor integrated circuit, and particularly a MOSFET, is miniaturized.
A semiconductor integrated circuit according to the present invention comprises: a semiconductor element having electrodes and a wiring layer formed on a separate layer from said electrodes. Only one of two mutually adjacent electrodes of the semiconductor element is divided into a plurality of portions that are formed on the same layer as the other electrode, and said divided parts are connected to said wiring layer.
When the semiconductor element is a MOSFET, the mutually adjacent electrodes are formed on a source diffusion layer and a drain diffusion layer. That is, they serve as the source electrode and drain electrode, respectively. The divided portions (split electrodes) are connected to the source diffusion layer or drain diffusion layer through a single contact hole. A silicide layer is also formed on the surface of the source diffusion layer or drain diffusion layer.
The electrodes and the wiring layers may be made of the same type of metal material, a candidate metal material being an aluminum-based metal film. Alternatively, the electrodes and the wiring layers may be formed of different metal materials, with the electrodes formed of an aluminum-based metal film and the wiring layers formed of a tungsten film.
Drain electrodes of a P-channel MOSFET and an N-channel MOSFET which constitute an inverter may be formed in a split manner. Namely, the drain electrode may be divided into a plurality of portions.
By thus dividing or splitting one of the electrodes constituting the semiconductor element, it is possible to reduce the parasitic capacitance produced between the mutually adjacent electrodes. When the semiconductor element is a MOSFET, it is also possible to reduce the parasitic capacitance produced between the gate electrode and the contact plug connecting the source or drain diffusion layer and the electrode. In addition, the parasitic capacitance is reduced and the operating speed of the semiconductor integra

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