Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-04-20

2002-12-24

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S194000, C327S141000

Reexamination Certificate

active

06498765

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as a semiconductor memory device, and more particularly to a clock-synchronous RAM and the like.
2. Description of the Background Art
FIG. 11
is a block diagram showing an overall constitution of an SRAM (SP-SRAM) with one read/write port. As shown in
FIG. 11
, the SP-SRAM consists of a word line driver
2
, an I/O circuit
3
, a memory cell array
4
, a timing generation circuit
6
and a delay circuit
7
.
The memory cell array
4
consists of a plurality of memory cells (not shown) arranged in matrix, and connected to a common word line (not shown) in a unit of row and connected to a common bit line (not shown) in a unit of column. The word line driver
2
receives a signal XDEC serving as a word line drive control signal, comes into an active state when the signal XDEC takes “H” (High Level), and selectively activates (opens) the word line on the basis of an externally-received address signal AD.
The I/O circuit
3
includes an input/output buffer, a sense amplifier, a write driver and a precharge circuit (all of which are not shown) therein. The sense amplifier comes into an active state when a sense amplifier activation signal SE takes “H”, and when in the active state, it detects and amplifies read data given from a selected memory cell in the memory cell array and externally outputs the data as output data. The write driver comes into an active state when a driver control signal WE takes “H”, when in the active state, it outputs write data based on externally-received input data to the selected memory cell through a pair of bit lines. The precharge circuit comes into an active state when a precharge control signal PC takes “H”, and when in the active state, it precharges the pair of bit lines in the memory cell array
4
to a predetermined potential.
The timing generation circuit
6
receives a clock signal CLOCK, a signal WEC and a signal READY and outputs the signal XDEC, the: signal SE, the signal WE, the signal PC and a signal DUM_XDEC all of which serve as control signals.
The delay circuit
7
outputs the signal READY of “L” (Low Level) after a delay time &Dgr;T
2
passes from the point of time when the signal DUM_XDEC changes from “H” to “L” and outputs the signal READY of “H” immediately after the signal DUM_XDEC changes from “L” to “H”. The delay time &Dgr;T
2
is so set as to satisfy both a time required to activate the word line in the memory cell array
4
and detect and amplify the read data by the sense amplifier in a read mode and a time required to store the write data given from the write driver into the selected memory cell in a write mode.
FIG. 12
is a circuit diagram showing an internal configuration of the timing generation circuit
6
shown in FIG.
11
. As shown in
FIG. 12
, inverters G
51
and G
52
are connected in series, and an input of the inverter G
51
receives the clock signal CLOCK. One input of a NAND gate G
54
receives an output from the inverter G
52
and the other input receives the signal READY. An input of an inverter G
56
receives an output from the NAND gate G
54
and an input of an inverter G
57
receives an output from the inverter G
56
.
On the other hand, an input of an inverter G
55
receives the signal READY. One input of a NAND gate G
58
receives an output from the inverter G
55
and the other input receives the output from the inverter G
52
. An input of an inverter G
59
receives an output from the NAND gate G
58
. One input of a NOR gate G
60
receives the signal XDEC and the other input receives an output from the inverter G
59
.
Further, an input of an inverter G
53
receives the signal WEC. One input of a NOR gate G
61
receives the signal WEC and the other input receives the output from the NAND gate G
54
. One input of a NOR gate G
62
receives an output from the inverter G
53
and the other input receives the output from the NAND gate G
54
. Inverters G
63
and G
64
are connected in series, and an input of the inverter G
63
receives an output from the NOR gate G
61
. Inverters G
65
and G
66
are connected in series, and an input of the inverter G
65
receives an output from the NOR gate G
62
.
An output of the inverter G
57
is outputted as the precharge control signal PC. An output of the inverter G
56
is outputted as the signal XDEC. An output of the NOR gate G
60
is outputted as the signal DUM_XDEC. An output of the inverter G
64
is outputted as the sense amplifier activation signal SE. An output of the inverter G
66
is outputted as the driver control signal WE.
FIG. 13
is a timing chart showing a generating operation of the timing generation circuit
6
shown in FIG.
12
. Referring to
FIG. 13
, the operation of the timing generation circuit
6
will be discussed below.
First, in an initial state, the signal XDEC is set to “L”, the signal READY is set to “H” and the signal DUM_XDEC is set to “H”. Further, it is assumed here that the timing generation circuit
6
is in a read mode with the write control signal WEC of “L”. In the read mode, the driver control signal WE is fixed to “L”.
In the initial state, when the clock signal CLOCK rises to “H”, the signal XDEC changes to “H” (change CH
11
) with rise of the clock signal CLOCK to “H” as a trigger since the signal READY takes “H”.
At the same time as the change CH
11
, the precharge control signal PC and the signal DUM_XDEC fall to “L” and the sense amplifier activation signal SE rises to “H”.
When the signal XDEC takes “H”, the word line driver
2
comes into an active state and selectively drives the word line (into the active state) on the basis of the externally-received address signal AD.
At the same time, the precharge circuit comes into an inactive state with the precharge control signal PC of “L”, and the sense amplifier comes into an active state with the sense amplifier activation signal SE of “H” to externally output the read data from the selected memory cell as the output data which is detected and amplified, starting a read operation.
Then, after the delay time &Dgr;T
2
passes from the rise of the signal XDEC (the fall of the signal DUM_XDEC), the signal READY falls to “L” (change CH
12
).
The signal XDEC falls to “L” (change CH
13
) with the fall of the signal READY to “L”. At the same time, the precharge control signal PC rises to “H” and the sense amplifier activation signal SE falls to “L”.
With the signal XDEC of “L”, the word line driver
2
comes into an inactive state to stop driving all the word lines, and with the sense amplifier activation signal SE of “L”, the sense amplifier comes into an inactive state, terminating the read operation. On the other hand, with the precharge control signal PC of “H”, a precharge operation on the pair of bit lines restarts.
Further, since the signal READY takes “L”, the signal DUM_XDEC sustains “L” even when the signal XDEC falls to “L”.
After that, when the clock signal CLOCK falls to “L”, the signal DUM_XDEC rises to “H” (change CH
14
) with fall of the clock signal CLOCK to “L” as a trigger.
Further, after the signal DUM_XDEC rises to “H”, the signal READY rises to “H” (change CH
15
) immediately. As a result, the signal XDEC comes into “L” and the signal READY and the signal DUM_XDEC come into “H”, returning to the initial state. After that, in synchronization with the clock signals CLOCK, the above operation is repeated.
Thus, the timing generation circuit
6
generates the signal XDEC, the precharge control signal PC and the sense amplifier activation signal SE all of which serve as the operation control signals, performing a timing control of the read operation.
Further, with the signal WEC of “H”, the timing generation circuit
6
comes into a write mode. Specifically, the timing generation circuit
6
generates the sense amplifier activation signal SE which is fixed to “L”, the driver control signal WE which changes like the sense amplifier activation signal SE in the read mode, and the signal XDEC and the precharge control signal Pc which change like

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