Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-07-13

2002-04-30

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S536000

Reexamination Certificate

active

06380792

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a switching circuit.
In a field of circuits for use in portable telecommunication equipment, lowering electric power is significantly required. In general, obstacles to lowering electric power of electronic equipment are MOS transistors (hereinafter, referred to as “MOS”) requiring large transconductance gm among components of the electronic equipment and an inverter or other logical gates. For example, in portable telecommunication equipment, a switch (hereinafter, referred to as “analog switch”) formed by the MOS is used for switching an input-output section for voice or other analog data, thereby obstructing lowering electric power.
As an example, a description will be made below for a semiconductor integrated circuit comprising an analog switch used for portable telecommunication equipment and its driver by referring to
FIG. 8. A
semiconductor integrated circuit
500
, as shown in
FIG. 8
, comprises an analog switch
510
for switching an input-output section for analog data and a driver
520
for driving the analog switch
510
.
The analog switch
510
comprises a P-channel MOS transistor (hereinafter, referred to as “PMOS”) M
1
and an N-channel MOS transistor (hereinafter, referred to as “NMOS”) M
2
. A source of the PMOS M
1
and a drain of the NMOS M
2
are connected to an input terminal T
1
to which analog data is inputted. A drain of the PMOS M
1
and a source of the NMOS M
2
are connected to an output terminal T
2
to which analog data is outputted. An analog switch
510
having this configuration is also referred to as a transfer gate and widely used for a formation of a switched capacitor filter (SCF) circuit or of an integrating circuit.
The driver
520
comprises a control signal input terminal T
3
to which a control signal is inputted for driving the analog switch
510
, inverters INV
1
and INV
2
connected in series to the input terminal T
3
, and an inverter INV
3
connected to the input terminal T
3
and connected in parallel to the inverters INV
1
and INV
2
. An output of the inverters INV
1
and INV
2
connected in series is connected to a gate G
1
of the PMOS M
1
. An output of the INV
3
is connected to a gate G
2
of the NMOS M
2
. A signal inputted to the input terminal T
3
is a supply voltage VDD at an H level or a ground voltage GND at an L level.
Logical levels are inverted between an output of the inverter INV
2
and an output of the inverter INV
3
which are outputs of the driver
520
. Normally an output of an inverter is at either the supply voltage VDD or the ground voltage GND, and therefore the supply voltage VDD is applied to one of the gate G
1
of the PMOS M
1
to which the output of the inverter INV
2
is applied and the gate G
2
of the NMOS M
2
to which the output of the inverter INV
3
is applied, while the ground voltage GND is applied to the other.
For example, if the input terminal T
3
is at the supply voltage VDD, the gate G
1
of the PMOS M
1
is at the supply voltage VDD and the gate G
2
of the NMOS M
2
is at the ground voltage GND, and therefore the analog switch
510
is not driven. If the input terminal T
3
is at the ground voltage GND, the gate G
1
of the PMOS M
1
is at the ground voltage GND and the gate G
2
of the NMOS M
2
is at the supply voltage VDD, and therefore the analog switch
510
is driven.
As described above, outputs of the inverters are at the supply voltage VDD or at the ground voltage GND. The transconductance gm of the MOS in this condition will be considered below. To consider the transconductance gm, drain current I
D
is described, first.
The drain I
D
of the MOS is expressed by the following equation (equation 1):
I
D
=&bgr;(
V
GS
−V
T
)
2
/2  (1)
where V
GS
is a gate-to-source voltage (also simply referred to as “gate voltage”), V
T
is a threshold voltage, and &bgr; is a constant proportional to dimensions of an MOS determined according to an effective channel length and an effective channel width of the MOS.
If the current I
D
expressed by the equation (1) is differentiated by the gate voltage V
GS
, the following equation is obtained:
gm=dI
D
/dV
GS
=&bgr;(
V
GS
−V
T
)  (2)
The characteristics of the MOS are represented by using the drain current I
D
or the transconductance gm. According to the equation (1) or (2), it is understood that the drain current is proportional to a square of the gate voltage V
GS
and that the transconductance gm is proportional to the gate voltage V
GS
.
In the semiconductor integrated circuit
500
, the gate voltage V
GS
is equal to the supply voltage VDD, and therefore the transconductance gm between the terminal T
1
and the terminal T
2
is decreased together with a reduction of the supply voltage VDD. Additionally in the above circuit configuration, it is understood that the transconductance gm of the analog switch is decreased when the supply voltage VDD reaches about the same voltage as (PMOS M
1
threshold value V
Tp
)+(NMOS M
2
threshold value V
Tn
) according to the equation (2).
Consideration will be given below for a case in which the supply voltage VDD is decreased from 2.0 V to 1.8 V when the threshold voltage V
Tp
of the PMOS M
1
is −0.8 V and the threshold voltage V
Tn
of the NMOS M
2
is 0.8 V, for example. If the supply voltage VDD is 2.0 V, (V
GS
−V
Tp
) of the PMOS M
1
equals −1−(−0.8)=−0.2 (V) and (V
GS
−V
Tn
) of the NMOS M
2
equals 1−0.8=0.2 (V). Subsequently when the supply voltage VDD is decreased to 1.8 V, (V
gs
−V
Tp
) of the PMOS M
1
equals −0.9−(−0.8)=−0.1 (V) and (V
gs
−V
Tn
) of the NMNOS M
2
equals 0.9−0.8=0.1 (V).
At this moment, as described above, the drain current I
D
of the MOS is proportional to a square of the gate voltage V
GS
and the transconductance gm is proportional to the gate voltage V
GS
, and therefore if the supply voltage VDD is lowered from 2V to 1.8 V, the drain current I
D
is decreased to (0.1/0.2)
2
=25(%) and the transconductance gm is decreased to (0.1/0.2)=50 (%).
As described above, when the supply voltage VDD is decreased to lower the voltage and the supply voltage VDD approaches (the threshold value V
Tp
of the PMOS M
1
) plus (the threshold value V
Tn
of the NMOS M
2
), it is required to secure the drain current I
D
and the transconductance gm of the MOS forming the analog switch. As a means for securing the transconductance gm, there is a method of increasing dimensions of the MOS to increase the constant &bgr; in the equation (2).
Increasing the dimensions of the MOS, however, increases a capacity among the gate, the drain, and the source, thereby increasing injected electric charges to generate big switching noises. Therefore, there has been a limitation on securing the transconductance gm by increasing the dimensions of the MOS.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit capable of achieving drain current and transconductance required for driving an analog switch even after lowering a supply voltage.
In order to accomplish the above object, the present invention provides a semiconductor integrated circuit comprising a transistor for a switch for transmitting an input signal given to one terminal to the other terminal according to a voltage given to a gate electrode, a boosting section for generating a higher voltage than a supply voltage, and an output section for giving the voltage generated by the boosting section to the gate electrode of the transistor for a switch.


REFERENCES:
patent: 5041739 (1991-08-01), Goto
patent: 5216290 (1993-06-01), Childers
patent: 5241502 (1993-08-01), Lee et al.
patent: 5552747 (1996-09-01), Tomasini et al.
patent: 5594380 (1997-01-01), Nam
patent: 5646571 (1997-07-01), Ohashi
patent: 6229740 (2001-05-01), Ogura

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