Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-06-12

2002-08-27

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S161000

Reexamination Certificate

active

06441665

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically, it relates to a clock supply technology employed to provide clock signals at the same phase to input/output circuits provided in the semiconductor integrated circuit.
2. Description of the Related Art
In parallel data transfer implemented between a plurality of semiconductor integrated circuits, data are normally input/output in synchronization with a reference clock signal. For instance, when inputting data in synchronization with the rise of the clock signal from level “L” to level “H,” the data to be transferred need to be sustained at a constant level over a specific length of time preceding and following the rise of the clock signal in order to transfer the data without error and with a high degree of reliability. The specific length of time elapsing before the rise is referred to as the setup time, whereas the specific length of time elapsing after the rise is referred to as the hold time.
As semiconductor integrated circuit technology has become more advanced, both the setup time and the hold time have been reduced to achieve a reduction in the length of time required for data transfer. However, unless clock signals achieving the same phase are provided to the input/output circuits utilized for data input/output, any reduction in the length of time required for data transfer is not achieved through reductions in the setup time and the hold time, in parallel data transfer. In other words, if the phases of clock signals provided to the individual input/output circuits are inconsistent, the actual data transfer cycle must be set by taking into consideration the inconsistency and, as a result, the length of time of data transfer increases.
At the same time, as the scale of integrated circuits is becoming larger, the routing through which clock signals are provided to the input/output circuits utilized for data input/output is becoming longer and more complex. In order to provide the clock signals to the individual input/output circuits while achieving uniform phase, methods such as devising a circuit arrangement that will equalize the lengths of supply routes and inserting a specific type of delay circuit in the clock supply route as necessary have been adopted in the prior art.
For instance,
FIG. 2
is a block diagram of the semiconductor integrated circuit in the prior art which is disclosed in Japanese Unexamined Patent Publication No. 1998-228449.
This semiconductor integrated circuit comprises a drive-side semiconductor device
10
that outputs data and a reception-side semiconductor device
20
that receives the data.
The drive-side semiconductor device
10
is provided with a clock source
11
and a shift clock generating circuit. The clock source
11
generates a clock signal CLK. The shift clock generating circuit
12
generates a shift clock signal SCK achieved by shifting the phase of the clock signal CLK by a specific degree. The clock signal CLK and the shift clock signal SCK are provided to a switch
13
where either one of the signals is selected a mode signal MOD provided from the outside.
The drive-side semiconductor device
10
is also provided with an internal logic circuit
14
and a dummy output generating circuit
15
. The internal logic circuit
14
generates output data. The dummy output generating circuit
15
generates dummy data to be used for adjustment. The output sides of the internal logic circuit
14
and the dummy output generating circuit
15
are connected to the input side of a switch
16
controlled by the mode signal MOD. The output side of the switch
16
is connected to the input sides of output circuits
17
-
0
~
17
-n, utilized to output in parallel data with a plurality of bits to the reception-side semiconductor device
20
. The output circuits
17
-
0
~
17
-n, output data in synchronization with the clock signal CLK or the shift clock signal SCK selected at the switch
13
.
The reception-side semiconductor device
20
is provided with a clock input circuit
21
and input circuits
22
-
0
~
22
-n. The clock signal CLK from the drive-side semiconductor device
10
is provided to the clock input circuit
21
, and the data with a plurality of bits are provided in parallel to the input circuits
22
-
0
~
22
-n. The clock input circuit
21
generates and provides an internal clock signal ICK required in the reception-side semiconductor device
20
by using the clock signal CLK. The internal clock signal ICK is provided to timing adjustment circuits
24
-
0
~
24
-n via a clock supply route
23
. The individual timing adjustment circuits
24
-
0
~
24
-n are respectively provided adjacent to the input circuits
22
-
0
~
22
-n, and are utilized to provide the internal clock signal ICK to the individual input circuits
22
-
0
~
22
-n, with almost the same timing by correcting differences in the length of transmission delay of the internal clock signal ICK occurring in the clock supply route
23
. The timing adjustment circuits
24
-
0
~
24
-n are each provided with a delay circuit that divides one cycle of the internal clock signal ICK into a plurality of equal portions, and the internal clocks ICK delayed by the individual delay circuits are sequentially selected to be provided to the corresponding input circuits
22
-
0
~
22
-n.
In this type of semiconductor integrated circuit, the mode signal MOD is set to an adjustment mode over a specific length of time in elapsing, for instance, immediately after a power-up. This results in the shift clock signal SCK being selected at the switch
13
of the drive-side semiconductor device
10
and the dummy output generating circuit
15
being selected at the switch
16
. As a result, dummy data for adjustment are output by the output circuits
17
-
0
~
17
-n in synchronization with a rise of the shift clock signal SCK.
At the clock input circuit
21
of the reception-side semiconductor device
20
, the internal clock signal ICK is generated based upon the clock signal CLK provided by the drive-side semiconductor device
10
and the internal clock signal ICK is provided to the timing adjustment circuits
24
-
0
~
24
-n via the clock supply route
23
. At the individual timing adjustment circuits
24
-
0
~-
24
-n, clock signals for timing adjustment output by the delay circuits are sequentially selected and provided to the corresponding input circuits
22
-
0
~
22
-n. Then, when the dummy data for adjustment provided by the output circuits
17
-
0
~
17
-n at the drive-side semiconductor device
10
have been input in a normal state, the timing of the clock signals output by the individual timing adjustment circuits
24
-
0
~
24
-n become fixed, thereby completing the timing adjustment for the clock signals.
When the specific length of time has elapsed after a power-up, the mode signal MOD is set in normal mode, thereby selecting the clock signal CLK at the switch
13
and selecting the internal logic circuit
14
at the switch
16
in the drive-side semiconductor device
10
. Thus, a normal operation starts in which data generated at the internal logic circuit
14
are output through the output circuits
17
-
0
~
17
-n in synchronization with a rise of the clock signal CLK.
At the individual input circuits
22
-
0
~
22
-n at the reception-side semiconductor device
20
, data input is performed in conformance to the clock signals provided by the individual timing adjustment circuits
24
-
0
~
24
-n having undergone adjustment.
However, the following problems have yet to be addressed in the semiconductor integrated circuit in the prior art.
Namely, the timing adjustment processing must always be performed over a specific period of time after power-up by setting the adjustment mode with the mode signal MOD, and thus, normal operation cannot be started for the specific length of time. In addition, it is necessary to implement control for performing the adjustment processing, which complicates the structure of the control circuit.
SUMMARY OF THE INVENTION
An obj

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2895331