Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-08-28

2002-03-12

Karlsen, Ernest (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010

Reexamination Certificate

active

06356095

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which a wafer test is performed to check functions of a plurality of input/output ports connected with a plurality of internal circuits.
2. Description of Related Art
FIG. 10
is a diagram showing a positional relationship among an internal circuit area and a plurality of input/output ports arranged around the internal circuit area in a conventional semiconductor integrated circuit. In
FIG. 10
,
101
indicates a rectangular-shaped semiconductor chip on which a conventional semiconductor integrated circuit is arranged, and
105
indicates a rectangular-shaped internal circuit area arranged in a central portion of the conventional semiconductor integrated circuit. A plurality of internal circuits such as logical circuits and an electric power supply circuit are arranged in the internal circuit area
105
.
104
indicates a plurality of input/output (I/O) ports, arranged on the four outer circumferential sides of the rectangular-shaped internal circuit area
105
, for respectively inputting external data to the corresponding internal circuit and outputting internal data produced in the corresponding internal circuit to the outside. Each input/output port
104
is composed of a wire-bonding pad (hereinafter, called a pad)
103
and a buffer
102
. Each pad
103
is connected with a bonding wire (not shown) in an normal operation to input or output data from/to an external apparatus (not shown) through the bonding wire.
106
indicates a probe. The probe
106
is connected with the pad
103
of each input/output port
104
in a wafer test. In the wafer test, an input test signal, an output test signal, various control signals and a voltage signal are transmitted between the probe
106
and each input/output port
104
to check a function of the corresponding internal circuit connected with the input/output port
104
.
An operation of the conventional semiconductor integrated circuit is described.
To check the function of each internal circuit (for example, each logical circuit) arranged in the internal circuit area
105
in the wafer test, the probe
106
is connected with the pad
103
of the input/output port
104
corresponding to the internal circuit, and the wafer test is performed. That is, an input test signal and various control signals supplied from the probe
106
are input to the internal circuit through the pad
103
and the buffer
102
of the input/output port
104
, and an output test signal produced in the internal circuit is output to the probe
106
through the input/output port
104
. Also, a voltage signal supplied from the probe
106
is input to a specific input/output port
104
used for the electric power supply to supply an electric power to the corresponding internal circuit.
However, because the probe
106
is connected with each of the pads
103
of the input/output ports
104
in the wafer test to check the functions of the internal circuits, there is a case where one pad
103
is damaged in the connection of the probe
106
with the pad
103
. In this case, even though a bonding wire is connected with the pad
103
in an normal operation, there is a problem that a contact failure occurs between the bonding wire and the pad
103
because the bonding wire is not electrically connected with the pad
103
.
Also, there is another conventional semiconductor integrated circuit in which a for-wafer-test pad exclusively used for the wafer test is additionally arranged for each input/output port
104
. In this conventional semiconductor integrated circuit, because a probe is connected with the for-wafer-test pad in the wafer test, the bonding wire can be reliably connected with the pad
103
in the normal operation without any connection failure. However, because a large number of input/output ports
104
are usually arranged in the conventional semiconductor integrated circuit, a large number of for-wafer-test pads are required, so that the size of the conventional semiconductor integrated circuit is considerably increased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional semiconductor integrated circuit, a semiconductor integrated circuit in which the occurrence of a contact failure between a bonding wire and a pad is prevented in the connection of the bonding wire with the pad in a normal operation performed after a wafer test while suppressing the increase of the size of the semiconductor integrated circuit having internal circuits.
The object is achieved by the provision of a semiconductor integrated circuit comprising a first for-wafer-test input/output element, exclusively used for a wafer test, for outputting a plurality of test signals to be used in the wafer test; a second for-wafer-test input/output element, exclusively used for the wafer test, for outputting a control signal to be used in the wafer test; a third for-wafer-test input/output element, exclusively used for a wafer test, for receiving the test signals used in the wafer test; and a plurality of input/output ports, which each correspond to an internal circuit and are serially arranged for a flow of the test signals output from the first for-wafer-test input/output element, for receiving the test signals serially output from the first for-wafer-test input/output element, outputting the test signals to the corresponding internal circuits according to the control signal received from the second for-wafer-test input/output element, reading out the test signals from the corresponding internal circuits according to the control signal and serially transferring the test signals to the third for-wafer-test input/output element according to the control signal.
In the above configuration, when the test signals are output to the corresponding internal circuits, a logical calculation or the like is performed for the test signal in each internal circuit to produce the test signal as a result of the logical calculation. Therefore, functions of the internal circuits can be checked in the wafer test by analyzing the test signals read out from the internal circuits. Also, because the test signals and the control signals are sent from the outside to the input/output ports through the first and second for-wafer-test input/output elements and because the test signals processed in the internal circuits are sent from the input/output ports to the outside through the third for-wafer-test input/output element, though a probe is connected with each for-wafer-test input/output element in the wafer test, no probe is connected with each input/output port in the wafer test.
Accordingly, each input/output port is not physically damaged in the wafer test, so that a bonding wire can be connected with each input/output port in a normal operation performed after the wafer test without any contact failure between the bonding wire and each input/output port. Therefore, the yield of the semiconductor integrated circuit can be improved.
Also, because the first, second and third for-wafer-test input/output elements are arranged in a set for all the input/output ports, the increase of the size of the semiconductor integrated circuit can be suppressed as compared with a case where one for-wafer-test input/output element is arranged for each input/output port.
It is preferred that each input/output port comprises a first shift register, the test signals serially output from the first for-wafer-test input/output element are held in the first shift registers of the input/output ports, the test signals held in the first shift registers are output to the corresponding internal circuits according to the control signal received from the second for-wafer-test input/output element, the test signals readout from the corresponding internal circuits according to the control signal are held in the first shift registers, and the test signals held in the first shift registers are transferred to the third for-wafer-test input/output elem

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2881877