Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-02-28

2002-01-15

Kim, Jung Ho (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S566000, C361S631000

Reexamination Certificate

active

06339358

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an improved circuit structure for reducing leakage current due to the subthreshold characteristic of a MOS transistor, to a semiconductor integrated circuit in which the operating voltage is kept constant, and to a technique which may be effectively applied to a large-capacity DRAM (Dynamic Random Access Memory) having a storage capacity of, for example, 256 Mbit to 1 Gbit or more.
In the case of an extremely-integrated semiconductor integrated circuit, such as a DRAM, the operating voltage is lowered to 2 to 2.5 V because elements are microminiaturized and the threshold voltage of a MOS transistor is lowered to 0.15 to 0.2 V (conventionally, approx. 0.4 V) to increase the operating speed. However, the leakage current (subthreshold current) due to the subthreshold characteristic of a MOS transistor is a problem. The subthreshold current is a leakage current which flows when the gate voltage is equal to or lower than a threshold voltage and the surface is weakly inverted.
A way of reducing the threshold voltage is disclosed in Japanese Patent Laid-Open Nos. 8-138381/1996, 6-232348/1994, 6-203558/1994, 5-210976/1993, and 5-347550/1993.
SUMMARY OF THE INVENTION
The present inventor has studied the application of a circuit for reducing the subthreshold current (Subthreshold Current Reduction Circuit: hereafter referred to as a SCRC) to a DRAM.
In
FIG. 16
, which illustrates an example of the SCRC previously studied by the present inventor, logic circuits L
1
to L
4
represented by a CMOS inverter are objects whose subthreshold current is to be reduced. The period for which the subthreshold current must be reduced is, e.g., the standby period for which the input signal IN inputted to the logic circuit L
1
is set to a low level (“L”). Thereby, to prevent a subthreshold current from being generated in MOS transistors Qn
1
, Qp
2
, Qn
3
, and Qp
4
, which are to be turned off in the standby state, sub-power supply lines SL
1
and SL
2
are provided, in addition to a main power supply line ML
1
to which a power supply voltage VDD is supplied and a main power supply line ML
2
to which a ground voltage VSS is supplied, a switch SD is provided between the main power supply line ML
1
and the sub-power supply line SL
1
, and a switch SS is provided between the main power supply line ML
2
and the sub-power supply line SL
2
. The switches SD and SS are controlled to be turned off in the standby state. When the switches SD and SS are turned off, the potential of the sub-power supply line SL
1
becomes lower than the power supply voltage VDD of the main power supply line ML
1
and the potential of the sub-power supply line SL
2
becomes higher than the ground voltage VSS of the main power supply line ML
2
. Thereby, a reverse bias is applied between the gate and source of each of the off MOS transistors Qn
1
, Qp
2
, Qn
3
, and Qp
4
in the logic circuits L
1
to L
4
, and the subthreshold current is reduced.
As a result of studying the above SCRC, the present inventor has found the following problems. The first problem of the SCRC is a voltage drop due to the wiring resistance of the power supply lines, particularly the sub-power supply lines. In the case of the SCRC, the number of power supply lines is doubled to 4. Therefore, it is an unavoidable necessity to reduce the width of each line from the aspect of the layout, and thereby the wiring resistance increases. When the potential of the sub-power supply line SL
1
on the power supply voltage VDD side is lowered due to the increased wiring resistance, and the potential of the sub-power supply line SL
2
on the ground voltage VSS side rises, the operating speed of a logic circuit is lowered in an operable state.
The second problem is the area occupied by the switches SS and SD. In the case of a MOS semiconductor integrated circuit, the switches SS and SD are actually realized by using MOS transistors. To prevent the operating speed of the logic gate from lowering, it is necessary to minimize the resistance while a switching MOS transistor is on. Thus, it is necessary to increase the channel width of the MOS transistor, and, thereby, the layout area is increased.
It is an object of the present invention to provide a semiconductor integrated circuit which is capable of reducing the voltage drop of a sub-power supply line for reducing the subthreshold current, thereby preventing the operating speed of the logic circuit from lowering.
It is another object of the present invention to provide a semiconductor integrated circuit which is capable of consuming less power in the wait state and realizing speed-up during the operating time.
The above and other objects and novel features of the present invention will become more apparent from the description of this specification and the accompanying drawings.
The outline of representative features of the present invention among the various features and aspects disclosed in this application will be briefly described below.
That is, a plurality of switching MOS transistors for selectively connecting a main power supply line to a sub-power supply wiring are dispersedly arranged on one main power supply line. It is possible to use the following mode for the layout of main power supply lines, sub-power supply lines, and switches.
Firstly, a main power supply line is provided along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply line. A plurality of switching MOS transistors for selectively electrically connecting a sub-power supply line with the main power supply line are dispersedly arranged on the main power supply line.
Secondly, the sub-power supply lines are arranged on the region in X and Y directions so that they intersect and are connected to each other at the intersections like a so-called mesh. In this case, the main power supply line is provided along one side or two adjacent sides of the region.
Thirdly, the switching MOS transistors for connecting the main power supply line to the sub-power supply lines are arranged in a region immediately below the main power supply line.
When dispersedly arranging the switching MOS transistors on the main power supply line as described above, it is possible to reduce the equivalent wiring resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place, because the distance between the MOS logic circuit whose subthreshold current must be reduced and the nearest switching MOS transistor is shortened. When MOS logic circuits whose subthreshold currents must be reduced are dispersed in the rectangular region, by arranging sub-power supply lines in the short side direction of the rectangular region, it is possible to use sub-power supply lines having a length equal to or less than the short side length of the rectangular region and thereby further reduce the resistance components of the sub-power supply lines. Moreover, by arranging sub-power supply lines like a mesh so that power is fed to them from two directions of the main power supply line along two adjacent sides of the rectangular region, the equivalent wiring resistance of the sub-power supply lines is further reduced.
When the equivalent wiring resistances of the sub-power supply lines are reduced, the voltage drop on the sub-power supply lines is reduced in the operable state of the MOS logic circuit. Therefore, even if the subthreshold current is reduced, it is possible to prevent the operating speed of the MOS logic circuit from lowering. Moreover, it is possible to further reduce the power consumption of a semiconductor integrated circuit in the wait state.
When the main power supply line comprises a first main power supply line to which a first power supply voltage having a relatively high level is applied and a second main power supply line to which a second power supply voltage having a relatively

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