Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1999-04-05

2002-09-24

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

C361S091100, C361S111000, C361S056000

Reexamination Certificate

active

06456474

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit provided with an overvoltage protection circuit for preventing breakdown due to static electricity.
2. Description of the Prior Art
A semiconductor integrated circuit has a structure in which a chip comprised of many semiconductor devices is stored in a package and a pin electrically connected to the chip protrudes beyond the package. When the semiconductor integrated circuit is sorted, packaged, carried, or operated, the chip is electrified positively or negatively due to contact with the exterior objects. Thereafter, when the pin contacts with an electric conductor, static electricity is discharged through a route from the chip to the pin and then the electric conductor. In this case, for example, a gate oxide film of an nMOS transistor of a first-stage input circuit may be broken down in the chip. This phenomenon is referred to as “breakdown due to CDM (Charge Device Model). ”
To prevent the breakdown due to CDM, it is necessary to prevent a potential difference from occurring between an input wiring and the ground wiring of the first-stage input circuit. Therefore, it is necessary to set an overvoltage protection circuit for absorbing the potential difference between the input wiring and the ground wiring of the first-stage input circuit.
FIG. 5
is an equivalent-circuit diagram showing the above conventional semiconductor integrated circuit. The semiconductor integrated circuit will be hereafter described by referring to FIG.
5
.
In case of a conventional semiconductor integrated circuit, a source electrode
52
s
of an nMOS transistor
52
constituting an first-stage input circuit
50
is connected to a ground wiring
54
and an overvoltage protection circuit
58
is connected between a ground wiring
56
and a gate electrode
52
g
of the nMOS transistor
52
. The overvoltage protection circuit
58
is comprised of a discharge device
581
having an nMOS transistor structure with which a gate electrode
581
g
and a source electrode
581
s
are connected and a discharge device
582
having an nMOS transistor structure with no gate electrode. In case of discharge devices
581
and
582
, their respective drain electrodes
581
d
and
582
d
are connected to the gate electrode
52
g
of the nMOS transistor
52
and their respective source electrodes
581
s
and
582
s
are connected to the source electrode
52
s
of the nMOS transistor
52
.
A pMOS transistor
60
is provided at the first-stage input circuit
50
. The gate electrodes
52
g
and
60
g
of the nMOS transistor
52
and the pMOS transistor
60
are connected with an input pad
62
by an input wiring
64
. Another overvoltage protection circuit
68
is connected between the ground wiring
56
and an input pad
62
. The overvoltage protection circuit
68
has a configuration almost same as that of the overvoltage protection circuit
58
but has a size different from that of the overvoltage protection circuit
58
and is comprised of discharge devices
681
and
682
. Parasitic resistances
54
r
and
56
r
denote resistance values of ground wirings
54
and
56
. A parasitic resistance
64
r
denotes a resistance value of the input wiring
64
. Moreover, the overvoltage protection circuit
68
protects the nMOS transistor
52
from an overvoltage (ESD) mainly applied to the input pad
62
. Contact holes
74
c,
64
c,
54
c,
58
dc,
58
gc,
561
c,
and
562
c,
a power-supply wiring
74
, and a ground pad
70
will be described later.
FIG. 6
is a top view showing the entire chip of the semiconductor integrated circuit of FIG.
5
. Hereafter, description is made by referring to
FIGS. 5 and 6
. In
FIG. 6
, a portion same as that of
FIG. 5
is provided with the same symbol and their duplicate description is omitted.
In the case of chip
69
, ground wirings
54
,
56
, and
66
are connected to each other nearby the ground pad
70
. Therefore, the parasitic resistance
54
r
denotes the resistance value of the ground wiring
54
from the first-stage input circuit
50
up to the ground pad
70
. The parasitic resistance
56
r
denotes the resistance value of the ground wiring
56
from the overvoltage protection circuit
58
up to the ground pad
70
. The ground wiring
54
is used for an first-stage input circuit, the ground wiring
56
is used for a protection circuit, and the ground wiring
66
is used for an internal cell. Moreover, a not-illustrated power-supply wiring is connected to a power-supply pad
72
.
FIG. 7
is a top view showing some of the wirings and diffusion layers of the semiconductor integrated circuit of FIG.
5
. Hereafter, description will be made by referring to
FIGS. 5
to
7
. In
FIG. 7
, however, a portion which is the same as those of
FIGS. 5 and 6
is provided with the same symbols and their duplicate description is omitted.
A p
+
layer
60
p
serving as a source region and a drain region is formed on a source electrode
60
s
and drain electrode
60
d
of the pMOS transistor
60
. An n
+
layer
60
n
serving as a guard ring is formed around the pMOS transistor
60
. An n
+
layer
52
n
serving as a source region and a drain region is formed on a source electrode
52
s
and a drain electrode
52
d
of the nMOS transistor
52
. A p
+
layer
52
p
serving as a guard ring is formed around the nMOS transistor
52
. n
+
layers
581
n
and
582
n
serving as a source region and a drain region are formed on the source electrodes
581
s,
582
s
and the drain electrodes
581
d
and
582
d
of the discharge devices
581
and
582
. A p
+
layer
58
P serving as a guard ring is formed around the discharge devices
581
and
582
.
The power-supply wiring
74
and the source electrode
60
s
are connected to each other by the contact hole
74
c.
The drain electrodes
60
d
and
52
d
are connected to each other. The ground wiring
54
and the source electrode
52
s
are connected each other by the contact hole
54
c.
The input wiring
64
and the gate electrodes
52
g
and
60
g
are connected each other by the contact hole
64
c.
The input wiring
64
and the drain electrodes
581
d
and
582
d,
etc. are connected each other. The ground wiring
56
and the source electrodes
581
s
and
582
s
are connected each other by the contact holes
561
c
and
562
c.
The source electrodes
581
s
and
581
g
are connected each other by the contact hole
58
gc.
Contact holes
60
sc,
60
dc,
52
sc,
52
dc,
581
sc,
582
sc,
and
58
dc
are used to connect each electrode with each semiconductor layer. The input wiring
64
, source electrodes
60
s,
52
s,
581
s,
and
582
s
and drain electrodes
60
d,
52
d,
581
d,
and
582
d,
etc. are formed by patterning the same electrode layer. The ground wirings
54
and
56
and the power-supply wiring
74
, etc. are formed by patterning the same wiring layer. The wiring layer is superimposed on the electrode layer through a not-illustrated insulating film. The contact holes
74
c,
54
c,
561
c,
and
562
c
are formed on the insulating film.
Then, operations of the overvoltage protection circuit
58
will be described below by referring to
FIGS. 5
to
7
.
It is assumed that a chip
69
is positively electrified due to static electricity and under this state, a pin (not illustrated) connected to the input pad
62
contacts an electric conductor. Then, the discharge devices
581
and
582
are turned on and static electricity is discharged through a route formed from the ground wirings
54
and
56
to the overvoltage protection circuit
58
and input pad
62
. In this case, an overvoltage is generated between the source electrode
52
s
and the gate electrode
52
g
of the nMOS transistor
52
. To protect the nMOS transistor
52
from the overvoltage, the overvoltage protection circuit
58
operates. That is, the discharge devices
581
and
582
are turned on to absorb the overvoltage between the source electrode
52
s
and the gate electrode
52
g.
Thus, the gate-electrode oxide film of t

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