Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-11-17

2002-05-28

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

C257S204000

Reexamination Certificate

active

06396087

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35USC §119 to Japanese Patent Application No. 1999-328525, filed on Nov. 18, 1999, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and, more particularly, to a circuit using different substrate potentials for power supply and ground voltages.
In some semiconductor integrated circuits, logic cells formed from transistors are regularly arranged, like standard cells or a gate array.
FIG. 1
shows the arrangement of a conventional semiconductor integrated circuit.
Power supply voltage VDD lines
1
and ground voltage Vss lines
2
are alternately wired on a semiconductor substrate at a predetermined interval along the lateral direction in FIG.
1
. Logic cells CA are arranged between the power supply voltage VDD lines
1
and the ground voltage Vss lines
2
along the lateral direction in
FIG. 1. A
vertical length Y of each logic cell CA in
FIG. 1
is determined constant by the interval between the power supply voltage VDD line
1
and the ground voltage Vss line
2
. A lateral length X in
FIG. 1
can be freely set in accordance with the area of each logic cell CA.
Each logic cell CA has a cell formed from transistors. A region
5
including the power supply voltage VDD line
1
receives a power supply voltage VDD. P-channel MOS transistors (referred to as P-channel transistors, hereinafter) are formed in the region
5
. A region
6
including the ground voltage Vss line
2
receives a ground voltage Vss. N-channel MOS transistors (referred to as N-channel transistors, hereinafter) are formed in the region
6
.
FIG. 2
shows the layout of an inverter made up of P- and N-channel transistors respectively formed in the regions
5
and
6
.
The region of each logic cell CA is present between the corresponding power supply voltage VDD and ground voltage Vss lines
1
and
2
. The power supply voltage VDD line
1
formed on the substrate through an insulating film and an n-type diffusion layer
3
formed in the surface portion of the substrate are connected through a contact hole
10
formed in the insulating film. The power supply voltage VDD is supplied to this n-type diffusion layer
3
.
The ground voltage Vss line
2
formed on the substrate via the insulating film, and the p-type diffusion layer
4
on the surface of the substrate are connected via the contact hole opened in the insulating film. The p-type diffusion layer is supplied with the ground voltage Vss.
The P-channel transistor
7
has a source region
25
, drain region
26
, and gate electrode
23
. The source region
25
is connected to the power supply voltage VDD line
1
through a VDD line
21
formed through an insulating film. The VDD line
21
and the power supply voltage VDD line
1
are connected through a first interconnection layer (single layer). The VDD line
21
is connected to the source region
25
through a contact hole
29
.
The N-channel transistor
8
has a source region
27
, drain region
28
, and gate electrode
24
. The source region
27
is connected to the ground voltage Vss line
2
through a ground line
22
formed through an insulating film. The ground line
22
and the ground voltage Vss line
2
are connected through a first interconnection layer (single layer). The ground line
22
is connected to the source region
27
through a contact hole
30
.
In the arrangement shown in
FIGS. 1 and 2
, the n-type substrate (n-type well) having the P-channel transistor
7
receives the same power supply voltage VDD as that supplied to the source of the transistor
7
. The p-type substrate (p-type well) having the N-channel transistor
8
receives the ground voltage Vss having the same potential as that supplied to the source of the transistor
8
. In recent years, however, a technique in which the source of the transistor and substrate potential are independently controlled to further improve the performance of the transistor layer has been used.
FIG. 3
shows the arrangement of a conventional semiconductor integration circuit in this case.
An n-type substrate potential NSUB line
11
a
and p-type substrate potential PSUB line
12
a
are arranged at positions adjacent to the power supply voltage VDD line
1
and ground voltage Vss line
2
, respectively, along the same direction. The n-type substrate potential NSUB line
11
a
supplies an n-type substrate potential NSUB to the n-type substrate having the P-channel transistor
7
through the contact hole
10
. The p-type substrate potential PSUB line
12
a
supplies a p-type substrate potential PSUB to the p-type substrate having the N-channel transistor
8
through a contact hole
12
.
The n-type substrate potential NSUB different from the power supply voltage VDD supplied to the source region
25
of the P-channel transistor
7
can be supplied to the n-type substrate. The p-type substrate potential PSUB different from the ground voltage Vss supplied to the source region
27
of the N-channel transistor
8
can be supplied to the p-type substrate.
Since, however, the n-type substrate potential NSUB line
11
a
and p-type substrate potential PSUB line
12
a
need be arranged at the positions adjacent to the power supply voltage VDD line
1
and ground voltage Vss line
2
, respectively, and the substrate potential lines
11
a
and
12
a
occupy a large area, thereby deteriorating area efficiency.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation, and has as its object to provide a semiconductor integrated circuit capable of supplying a potential different from that of the source of a transistor to a substrate and improving area efficiency.
According to the present invention, a semiconductor integrated circuit is provided, in which a plurality of cells are arranged in a cell region on a substrate and each of the cells has a first power supply line for supplying a first voltage (corresponding to either of the power supply voltage VDD and the ground voltage Vss in the embodiments) to the cell and a second power supply line for supplying a second voltage (corresponding to either of the power supply voltage VDD and the ground voltage Vss in the embodiments) to the cell, comprises:
a first substrate potential line having a first substrate potential;
a second substrate potential line having a second substrate potential; and a substrate potential supply cell arranged in the cell region and connected to the first and second substrate potential lines to supply the first and second substrate potentials to the substrate in accordance with a conductivity type of the substrate.
In this case, the substrate potential supply cell may be arranged at a position on the basis of a design standard about a distance between an element formed in the cell and a region for supplying the first and second substrate potentials to the substrate.
To supply the first and second substrate potentials different from the first and second voltages to the substrate, the semiconductor integrated circuit according to the present invention has the following arrangement. In place of wiring the first and second substrate potential lines in one direction in the logic cell region, the substrate potential supplying cell is arranged in the logic cell region, and the first and second substrate potentials are supplied to the substrate using this cell, thereby increasing the element area.
Also, according to the present invention, a semiconductor integrated circuit is provided, in which a plurality of cells are arranged in a cell region on a substrate and each of the cells has a first power supply line for supplying a first voltage to the cell and a second power supply line for supplying a second voltage to the cell, comprising:
a substrate potential line having a substrate potential; and
a substrate potential supply cell arranged in the cell region and connected to the substrate potential line to supply the substrate potential to the substrate.

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