1988-03-07
1991-04-02
Laroche, Eugene R.
357 74, H01L 2934, H01L 2302, H01L 2312
Patent
active
050050672
ABSTRACT:
A semiconductor integrated circuit providing a novel patterned multilayered wiring structure to enhance the degree of the integration of the circuit and the speed of the operation. The structure includes at least one first interlaid electric insulator film on the wall of the contact portion of a first wiring layer and its vicinity, a second interlaid electric insulator film, which reacts distinctly to the etching process utilized from the first interlaid electric insulator film, is provided on a substrate.
REFERENCES:
patent: 3892608 (1975-07-01), Kuhn
patent: 4755479 (1988-07-01), Miura
Iwamori Toshimichi
Sakata Yasushi
Fuji 'Xerox Co., Ltd.
LaRoche Eugene R.
Shingleton Michael B.
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