Semiconductor integrated circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase

Reexamination Certificate

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Details

C327S002000, C327S012000, C327S172000

Reexamination Certificate

active

08008946

ABSTRACT:
A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal.A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the clock signal. A first line transfers the first signal, while a second line transfers the second signal. A phase comparator is connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units.A plurality of the phase comparators are connected to the first line and the second line, and are disposed between one of the ends of the first line and the second line and one of the circuit units.

REFERENCES:
patent: 7049867 (2006-05-01), Kinugasa et al.
patent: 2006/0087346 (2006-04-01), Ishida et al.
patent: 52-149949 (1977-12-01), None
patent: 63-6329 (1988-01-01), None
patent: 03-224020 (1991-10-01), None
patent: 05-259846 (1993-10-01), None
patent: 06-163827 (1994-06-01), None
patent: 06-350439 (1994-12-01), None
patent: 07-177004 (1995-07-01), None
patent: 11194848 (1999-07-01), None
patent: 11-355107 (1999-12-01), None
patent: 2000-278103 (2000-10-01), None
Japanese Office Action for 2008-199131 mailed on Dec. 7, 2010.

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