Semiconductor integrated circuit

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S184000

Reexamination Certificate

active

07876641

ABSTRACT:
A clock signal generation circuit into which a first clock signal and a control signal based on an address are inputted, and a second clock signal based on said first clock signal is generated after a lapse of predetermined time from said input of the control signal.

REFERENCES:
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patent: 2001/0002181 (2001-05-01), Kim et al.
patent: 2004/0109382 (2004-06-01), Chung et al.
patent: 2005/0002259 (2005-01-01), Suyama
patent: 2009/0129196 (2009-05-01), Sasaki
United Kingdom Patent Office issued an United Kingdom Office Action dated Feb. 19, 2009, Application No. GB0819936.6.
L220 Cache Controller Technical Reference Manual, Revision: r1p7, http://infocenter. arm.com/help/topic/com.arm.doc.ddi0329i/DDI0329.pdf), 2004-2007.

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