Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-04-27

2001-02-20

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230090, C365S239000

Reexamination Certificate

active

06192004

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for outputting data signals read from memory cells at a plurality of times during one cycle of a clock signal and, more particularly, to a technology for outputting the data signals at high speed.
2. Description of the Related Art
Recently, the SDRAM (Synchronous DRAM) or the like has been developed as a semiconductor integrated circuit for outputting data signals at high speed by operating an input/output interface at high speed in synchronization with a clock signal or the like. The DDR-SDRAM (Double Data Rate Synchronous DRAM) has also been developed as a semiconductor integrated circuit for outputting data in synchronization with each rise of complementary clock signals (or both a rise and a fall of a clock signal).
FIG. 1
shows an example of the construction of such an output controlling unit
1
of the semiconductor integrated circuit of the kind as to control the output of the data signal of the DDR-SDRAM.
The output controlling unit
1
comprises a clock pulse generator
2
, a read controlling circuit
3
, an output enable switching circuit
4
, a data transmitting circuit
5
, a data switching circuit
6
, and a data output circuit
7
.
The clock pulse generator
2
receives clock signals CLKZ and CLKX and outputs clock pulses OCLKPZ and OCLKPX respectively in synchronization with the rises of the clock signals CLKZ and CLKX. These clock signals CLKZ and CLKX are signals which have received complementary external clock signals CLK and /CLK (not shown) supplied from the exterior by a clock buffer.
The read controlling circuit
3
includes a latency counter
8
, a latency controlling circuit
9
and a data converting pulse switching circuit
10
.
The latency counter
8
receives the clock pulse OCLKPZ and a read controlling signal RDPZ, outputs latency delay signals LAT
30
Z and LAT
40
Z. The read controlling signal RDPZ changes to a high level during a predetermined period when a read command is received from the exterior.
The latency controlling circuit
9
receives the clock pulse OCLKPX, the latency delay signals LAT
30
Z, LAT
40
Z and latency controlling signals DL
40
Z, DL
45
Z and outputs output controlling signals OE
30
Z, POE
35
Z, and POE
40
Z.
The latency controlling signals DL
40
Z and DL
45
Z are generated according to the set value of a mode register(not shown). When the mode register is set at “latency 4”, for example, the latency controlling signal DL
40
Z changes to a high level and the latency controlling signal DL
45
Z changes to a low level. When the mode register is set at “latency 4.5”, the latency controlling signal DL
40
Z changes to the low level and the latency controlling signal DL
45
Z changes to the high level. Here, the “latency” is a number of clock cycles from the receipt of the read command to the start of outputting the data. In the read operation after the writing operation, for example, by setting the “latency” at a number which is divisible by 0.5, the period during which a data signal DQ is not to be transmitted is minimized so that the usage rate of the data bus can be increased.
The data converting pulse switching circuit
10
receives the clock pulses OCLKPZ and OCLKPX, the output controlling signal OE
30
Z and the latency controlling signals DL
40
Z and DL
45
Z, and outputs data converting pulses PSCLKLN and PSCLK
2
N.
The output enable switching circuit
4
receives the output controlling signals, POE
35
Z and POE
40
Z and the latency controlling signals DL
40
Z and DL
45
Z, and outputs the output controlling signals OE
30
Z, POE
35
Z and POE
40
Z.
The data transmitting circuit
5
receives data signals CDB
01
X and CDB
02
X, as read from the memory cells(not shown), and the data converting pulses PSCLK
1
N and PSCLK
2
N, and outputs data signals DT
1
Z and DT
2
Z.
The data switching circuit
6
receives the data signals DT
1
Z, DT
2
Z and the latency controlling signals DL
40
Z, DL
45
Z, and outputs data signals PSDT
1
Z and PSDT
2
Z.
The data output circuit
7
receives the clock pulses OCLKPZ and OCLKPX, the output controlling signals OE
35
Z and OE
40
Z, and the data signals PSDT
1
Z and PSDT
2
Z, and outputs a data signal DOUT to a pad PAD.
FIG. 2
shows a detail of the clock pulse generator
2
.
The clock pulse generator
2
comprises identical pulse generators
11
a
and
11
b
. The pulse generator
11
a
has a delay circuit
12
a
for generating a delay signal CLKDZ inverted and delayed from the clock signal CLKZ, and a 2-input AND gate
12
b
for receiving the clock signal CLKZ and the delay signal CLKDZ and generating the clock pulse OCLKPZ. In the delay circuit
12
a
, there are arranged CR time constant circuits
12
c
between five inverters connected in cascade. The CR time constant circuit
12
c
includes a diffusion resistor R
1
and a MOS capacitor C
1
connecting the source and drain of an nMOS with a grounded line VSS. The pulse generator
11
b
receives the clock signal CLKX and generates the clock pulse OCLKPX. The clock pulse generator
2
generates clock pulses OCLKPZ and OCLKPX in synchronization with the rises of the clock signals CLKZ and CLKX.
FIG. 3
shows a detail of the latency counter
8
.
This latency counter
8
includes three latch circuits
13
a
,
13
b
, and
13
c
connected in cascade, and a plurality of inverters.
Each of the latch circuits
13
a
,
13
b
, and
13
c
has a cascade connection of: a CMOS transmission gate
15
to be turned on when the clock pulse OCLKPZ is at the low level; a latch
16
including an inverter
16
a
the input and output of which are connected with the output and input of a clocked inverter
16
b
; a CMOS transmission gate
17
to be turned on when the clocked pulse OCLKPZ is at the high level; and a latch
18
having two inverters connected with each other at their inputs and outputs.
The CMOS transmission gates
15
and
17
are formed by connecting the sources and drains of nMOS and pMOS with each other. A pMOS
16
c
of the clocked inverter
16
b
formed on the feedback side of the latch
16
receives at its gate the inverted signal of the clock pulse OCLKPZ, and an nMOS
16
d
receives at its gate a signal of the same logic as that of the clock pulse OCLKPZ. The latches
13
a
,
13
b
and
13
c
are circuits for accepted signals when the clock pulse OCLKPZ is at the low level, and outputting the accepted signals when the clock pulse OCLKPZ is at the high level. The input of the latch circuit
13
a
receives the read controlling signal RDPZ. The latch circuit
13
b
outputs the latency delay signal LAT
30
Z. The latch circuit
13
c
outputs the latency delay signal LAT
40
Z. In other words, the latency counter
8
raises the latency delay signals LAT
30
Z and LAT
40
Z to the high level in synchronization with the rises of the third clock and the fourth clock of the clock pulse OCLKPZ after the receipt of a read command.
FIG. 4
shows a detail of the latency controlling circuit
9
.
This latency controlling circuit
9
includes: latch circuits
19
a
and
19
b
; CMOS transmission gates
20
a
,
20
b
and
20
c
to be turned on when the latency controlling signal DL
40
Z is at the high level; CMOS transmission gates
21
a
,
21
b
and
21
c
to be turned on when the latency controlling signal DL
45
Z is at the high level; and a plurality of inverters. The latch circuits
19
a
and
19
b
are identical to the latch circuit
13
a
of FIG.
3
. The latch circuit
19
a
receives the latency delay signal LAT
30
Z, the inverted signal of the clock pulse OCLKPZ and a signal of the same logic as that of the clock pulse OCLKPZ and outputs the latency delay signal LAT
35
Z delayed by a half clock from the latency delay signal LAT
30
Z. The latch circuit
19
b
receives the latency delay signal LAT
40
Z, the inverted signal of the clock pulse OCLKPZ and a signal of the same logic as that of the clock pulse OCLKPZ, and outputs the latency delay signal LAT
45
Z delayed by a half clock from the latency delay signal LAT
40
Z.
The CMOS transmission gate

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