Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-01-28

2001-08-07

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S080000, C327S309000, C365S201000

Reexamination Certificate

active

06271692

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to enabling switching over from a normal operating mode to an internal circuit test mode by using an input terminal inputted with an input signal used during normal operation of the internal circuit within the semiconductor integrated circuit as a terminal for inputting a high-voltage (a voltage higher than the input signal voltage used during normal operation) test signal during testing (hereinafter referred to as internal circuit testing) such as reading and writing, for example, internal memory data prior to shipping the semiconductor integrated circuits as products. The present invention relates to a semiconductor integrated circuit equipped with a protection circuit having a superior protection function where this switching circuit is implemented without increasing the surface area of the semiconductor chip.
2. Description of the Related Art
Conventionally, in semiconductor integrated circuits that test internal circuits using a higher voltage than the input signal voltage used during normal operation of the internal circuit, there is provided a protection circuit where a P-type MOS transistor is connected across a node of a signal line connecting the input terminal and the internal circuit and a power supply voltage, and an N-type MOS transistor connected across the node and an earth voltage. With this semiconductor integrated circuit, a voltage determining circuit for determining whether a voltage for normal operation of the semiconductor integrated circuit or a high voltage (10V) for switching over to operating mode is inputted to the input terminal is connected between the node and the internal circuit. In this kind of protection circuit, the gate electrode of the P-type MOS transistor is connected to the substrate and a pad for high voltage use, and the gate electrode of an N-type MOS transistor is connected to the substrate voltage and an earth voltage.
With semiconductor integrated circuits equipped with this kind of protection circuit, when a voltage applied to the input terminal is an abnormal voltage higher than a voltage (for example, 10V) for switching the operating mode over to internal circuit testing, this high voltage is drawn from a high-voltage pad via a P-type transistor. On the other hand, when the voltage applied to the input terminal is an abnormal voltage (low voltage) lower than an earth voltage (for example, 0V,), this low voltage is drawn from the earth voltage via an N-type MOS transistor. As a result, application of an abnormal voltage (high voltage or low voltage) to the internal circuit and damage to the internal circuit is prevented.
However, with related semiconductor integrated circuits equipped with a protection circuit, a high voltage (for example, 10V) pad connected to the gate electrode and substrate of the P-type MOS transistor has to be provided in order to protect the internal circuit from abnormal voltages (high voltages in excess of 10V). However, when this high-voltage pad is provided, it is also necessary to provide a protection transistor to protect the high voltage pad itself and this increases the surface area of the semiconductor chip. On the other hand, when the gate electrode and substrate potential of the P-type MOS transistor are connected to the power supply voltage (for example, 5V) used during normal operation of the internal circuit in order to prevent increases in the semiconductor chip surface area, this voltage is drawn from the power supply voltage side via the P-type MOS transistor when a high voltage (for example, 10V) is inputted when switching over to internal circuit testing mode and switching over to internal circuit testing mode therefore becomes difficult.
In the related technology described above, the withstand voltage of a transistor having a protection function falls with increasing speed in the operation of elements of the semiconductor integrated circuit. N-type MOS transistors (earth voltage side protection transistors), where the potential difference between values (for example, 0V to 10V) of input signal voltages used during normal operation of the internal circuit and used during switching over to internal circuit test mode is large, can therefore become damaged as the withstand voltage of the transistor becomes lower. As a result, the value of the input signal voltage used during switching to internal circuit test mode may fall and setting of the desired operating mode may become difficult.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor integrated circuit which has a superior protection function whilst remaining small.
In order to achieve the aforementioned object, the semiconductor integrated circuit of the present invention comprises an internal circuit supplied with a power supply voltage, an input terminal connected to the internal circuit by a signal line, a first P-type MOS transistor having a gate electrode, first electrode and substrate connected to the power supply voltage, and a second electrode, and a second P-type MOS transistor having a third electrode connected to the second electrode of the first P-type MOS transistor and a fourth electrode, substrate and gate electrode connected to the signal line.
In order to achieve the aforementioned object, a further semiconductor integrated circuit of the present invention comprises an internal circuit supplied with a power supply voltage, an input terminal connected to the internal circuit by a signal line, a first N-type MOS transistor having a first electrode connected to the power supply voltage, a second electrode connected to the signal line, and a gate electrode and substrate connected to the earth voltage; and a second N-type MOS transistor having a third electrode connected to the signal line via a resistor, and a fourth electrode, gate electrode and substrate connected to the earth voltage.
In order to achieve the aforementioned object, a still further semiconductor integrated circuit of the present invention comprises an internal circuit supplied with a power supply voltage, an input terminal connected to the internal circuit by a signal line, a first N-type MOS transistor having a first electrode connected to the power supply voltage, a second electrode connected to the signal line, and a gate electrode and substrate connected to the earth voltage, a second N-type MOS transistor having a third electrode connected to the signal line, a fourth electrode, a gate electrode connected to the earth voltage, and a substrate connected to the fourth electrode, and a third N-type MOS transistor having a fifth electrode connected to the fourth electrode, and a sixth electrode, gate electrode and substrate connected to the earth voltage.


REFERENCES:
patent: 5525933 (1996-06-01), Matsuki et al.
patent: 6081152 (2000-06-01), Maley
patent: 5-199097 (1993-08-01), None
patent: 7-240678 (1995-09-01), None
patent: 8-125033 (1996-05-01), None
patent: 8-222643 (1996-08-01), None
patent: 8-288404 (1996-11-01), None

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