Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1999-04-06

2001-08-14

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C324S1540PB, C714S728000, 37

Reexamination Certificate

active

06275055

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit to which a DC test for checking of leakage from input pins or of output voltage level can be performed by using a tester having a smaller number of pins than a number of pins in a semiconductor integrated circuit.
BACKGROUND OF THE INVENTION
A test for a semiconductor integrated circuit (described LSI hereinafter) is largely classified to a function test for checking a logical function for the circuit and a DC test for checking of leakage from an input pin or of output voltage level. Those tests are generally performed by using a commercially available tester (described an LSI tester hereinafter).
FIG. 11
is a simulated view showing a connectional relation between a conventional type of LSI and LSI tester. The LSI tester
1
comprises pin electronics
11
enabling generation and monitoring of signal waveforms for performing a function test, a DC measuring unit
12
provided separately from the pin electronics
11
for DC measurement, and relays
14
provided at midpoint of signal lines
13
respectively.
When a function test is performed, the relays
14
are switched to the pin electronics
11
, by which the signal pins
21
of the LSI
2
are connected to the pin electronics
11
of the LSI tester
1
through the relays
14
so that the signal pins
21
are in one-to-one correspondence with the pin electronics
11
.
On the other hand, when a DC test is performed, the relays
14
are successively switched to the DC measuring unit
2
one after another. With this operation, the signal pins
21
of the LSI
2
are successively connected to the DC measuring unit
12
through each relay
14
switched to the DC measuring unit
12
.
FIG. 11
shows a state where the topmost signal pin
21
of the LSI
2
is connected to the DC measuring unit
12
.
Description is made herein for the DC test. The DC test has three types of tests: a pin contest for checking connection between the LSI tester and LSI, an input leak test for checking whether there is failure as current leakage to an input pin of the LSI, and an output voltage test for checking a voltage level output from an output pin of the LSI.
FIG. 12
is a view showing an outline of the pin contest, and the reference numerals Dl and D
2
show protective diodes provided in the power unit VDD and a ground GND of the signal pin section in the LSI
2
respectively. In the pin contest a voltage V
1
being generated in the protective diode Dl when a current I
1
is supplied to the LSI
2
through the signal pin
21
from the DC measuring unit
12
of the LSI tester
1
and a voltage V
2
being generated in the protective diode D
2
when a current I
2
is taken out from the LSI
2
is measured, and connection between the LSI tester
1
and LSI
2
are checked according to those measured values.
FIG. 13
is a view showing an outline of the input leak test. The input leak test provides a potential at a relatively lower level (corresponding to “0”) or at a relatively higher level (corresponding to “1”) to the signal pin
21
of the LSI
2
using the DC measuring unit
12
, and checks the current flowing at that point of time. When there is resistive short-circuiting failure to the power unit VDD (shown as resistance R
1
in FIG.
13
), a current I
3
flows into the LSI tester
1
when “0” is provided to the signal pin
21
, and when there is resistive short-circuiting failure to the ground GND (shown as resistance R
2
in FIG.
13
), a current I
4
flows into the LSI
2
when “1” is provided to the signal pin.
FIG. 14
is a view showing an outline of the output voltage test, and in this test, a current I
5
is drawn out to the LSI tester
1
when the voltage output from the signal pin is “1”, on the other hand, when voltage output from the signal pin is “0”, a voltage level is checked while a current I
6
is provided to the LSI
2
. Assuming that resistance of the gate G
1
is Rp when it becomes ON when the output voltage is “1”, the voltage when this gate G
1
is ON can be expressed with the following expression (1), and assuming that resistance of the gate G
2
is Rn when it becomes ON when the output voltage is “0”, the voltage when this gate G
2
is ON can be expressed with the following expression (2).
Voltage=VDD−Rp×|I
5
|  (1)
Voltage=Rn×|I
6
|  (2)
The output voltage test checks whether the values of Rp and Rn according to the expressions (1) and (2) are within a normal range or not.
The scale of integration in LSI is dramatically becoming larger in recent years, and in association with that number of signal pins is becoming larger, and therefore there has arisen a case where the number of signal pins of the LSI exceeds the number of pin electronics prepared for the existing LSI tester. In that case, in the conventional type of LSI tester, there may occur a problem that some signal pins in the LSI can not be connected to the LSI tester, so that it is difficult to test the LSI, but it is possible to perform the function test by incorporating self-test capabilities inside the LSI in place of the conventional method using the LSI tester. In this case, only some signal pins are sufficient for inputting a clock signal and a control signal into the LSI from the outside.
As for the DC test, however, there is no solution so far for a case where a number of signal pins of LSI is larger than a number of pin electronics of an LSI tester, and therefore the DC test can not be performed.
SUMMARY OF THE INVENTION
It is an object of the present invention to obtain, for solving the problems described above, a LSI (semiconductor integrated circuit) which can be DC tested using a LSI tester having a smaller number of pins than a number of signal pins in the LSI.
With the present invention, a LSI to which a DC test is performed by a tester connected to the outside thereof has a plurality of switches successively becoming ON at the time of DC testing in signal paths between a plurality of internal circuits for signal input/output and a signal pin for a DC test respectively, and by turning ON each switch, the plurality of internal circuits are successively connected to the signal pin for a DC test one by one when the DC test is performed.
With the present invention, an internal circuit comprises protection diodes and an input buffer circuit or an output buffer circuit connected thereto.
With the present invention, a switch comprises a transfer gate.
With the present invention, a register is incorporated therein as a circuit for generating signals for successively turning ON the switches, and the register shifts an ON signal of the switches and successively outputs to each of the switches.
With the present invention, a current path with parasitic diodes is cut off by an N-channel transistor when the DC test is performed.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.


REFERENCES:
patent: 5640102 (1997-06-01), Sato
patent: 5701306 (1997-12-01), Arai
patent: 6076178 (2000-06-01), Komoda
patent: 5-256910 (1993-10-01), None
patent: 6-300814 (1994-10-01), None
patent: 10-48289 (1998-02-01), None

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