Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of...
Reexamination Certificate
1999-03-02
2001-05-01
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
C438S318000, C438S324000, C438S365000, C438S369000, C438S371000, C438S509000
Reexamination Certificate
active
06225179
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated bi-MOS circuit and a process for fabricating the semiconductor integrated bi-MOS circuit device on a single semiconductor substrate.
DESCRIPTION OF THE RELATED ART
A static random access memory device is a typical example of the semiconductor integrated circuit device. Various circuit configurations for the static random access memory device are known. A high-speed static random access memory device is, by way of example, implemented by a combination of bipolar transistors and field effect transistors. The high-speed static random access memory cell has a field effect transistor, the polysilicon gate electrode of which is of the order of 0.3 micron in width. Such a short channel length affects the high-frequency characteristics of the associated bipolar transistor.
The manufacturer takes two approaches in order to improve the high-frequency characteristics of the bipolar transistor. First, the manufacturer increases the thickness of the oxide layer under the emitter electrode, and the thick oxide layer reduces the parasitic capacitance. Second, the manufacturer decreases the gate oxide layer of the field effect transistor, and the thin gate oxide layer improves the switching action of the field effect transistor.
The bipolar transistor and the field effect transistor are fabricated through the following sequence. First, the thin gate oxide layer of the order of 8 nanometers thick is grown on a semiconductor substrate, and the narrow polysilicon gate electrode is patterned on the thin gate oxide layer. Dopant impurity is ion implanted into the semiconductor substrate, and forms source/drain regions in a self-aligned manner with the narrow polysilicon gate electrode. Subsequently, the thick oxide layer of 100-200 nanometers thick is formed, and the bipolar transistor is fabricated. Namely, a base region is formed, and en emitter region is formed in the base region through diffusion from an emitter electrode passing through an emitter contact hole formed in the thick oxide layer.
However, the manufacturer encounters a problem in the prior art process sequence in the punch-through phenomenon. This is because of the fact that the manufacturer applies heat to the resultant semiconductor structure for forming the emitter region after the completion of the source/drain regions. The dopant impurity is diffused from the source/drain regions into the channel of the order of 0.3 micron in length, and the punch-through phenomenon is liable to take place. If the diffusion is carried out at low temperature for short time, the dopant concentration in the emitter region is too low to achieve large current amplification factor. Thus, there is a trade-off between the punch-through phenomenon and the low current amplification factor.
In order to prevent the field effect transistor from the punch-through phenomenon without reduction of the current amplification factor, the manufacturer uses another prior art process. The bipolar transistor is firstly fabricated on a semiconductor substrate, and, thereafter, fabrication of the field effect transistor follows. Even tough the emitter region is formed through a high-temperature long-time diffusion, the high-temperature long-time diffusion does not affect the impurity profile of the source/drain regions. The source/drain regions are, thereafter, formed through a low-temperature short-time heat treatment.
FIGS. 1A
to
1
D illustrate the prior art process for fabricating a bi-CMOS circuit. Description is focused on a bipolar transistor and an n-channel enhancement type field effect transistor, and description on a p-channel enhancement type field effect transistor is omitted hereinbelow for the sake of simplicity.
The process starts with preparation of a silicon substrate
1
. First, phosphorous is ion implanted into a surface portion of the silicon substrate
1
at dosage of 5E11 to 1E1012 atom/square-cm under acceleration energy of 70-100 KeV, and forms a lightly-doped n-type collector region
3
.
Subsequently, silicon oxide is selectively grown to 400 nanometers thick on the major surface by using the LOCOS (Local Oxidation of Silicon) technique, and forms a thick field oxide layer
4
. The thick field oxide layer
4
defines an active area assigned to a bipolar transistor and another active area assigned to a field effect transistor.
A photo-resist ion-implantation mask (not shown) is formed on the major surface by using photo-lithographic techniques, and has an opening over a region assigned to a heavily-doped n-type collector contact region
5
, and phosphorous is ion implanted into the region at dosage of 5E15 to 1E16 atom/square-cm under acceleration energy of 70-100 KeV. The photo-resist ion-implanted mask is stripped off. The ion-implanted phosphorous is activated at 950-1000 degrees in centigrade for 30-45 minutes. As a result, the heavily-doped n-type collector contact region
5
is formed in the lightly-doped n-type collector region
3
.
A photo-resist ion-implantation mask (not shown) is formed on the major surface by using the photo-lithographic techniques, and has an opening over the active area assigned to the bipolar transistor. Phosphorous is ion implanted into the active area at dosage of 3E13 to 5E13 atom/square-cm under acceleration energy of 1000-1200 KeV, and the photo-resist ion-implantation mask is stripped off after the ion-implantation. The phosphorous are activated at 950-1000 degrees in centigrade for 10-20 minutes, and forms an n-type buried layer
6
. The n-type buried layer
6
is connected to the heavily-doped n-type collector contact region
5
.
Subsequently, an ion-implantation mask (not shown) is formed on the major surface by using the photo-lithographic techniques, and has an opening over the active areas assigned to the field effect transistors. Boron is ion implanted into the active areas at dosage of 1E13 to 2E13 atom/square-cm under acceleration energy 250-300 KeV, and a channel doping is carried out for n-channel enhancement type field effect transistors. The photo-resist ion-implantation mask is stripped off. The boron forms a p-type well
7
.
Subsequently, an ion-implantation mask (not shown) is formed on the major surface by using the photo-lithographic techniques, and has an opening over the lightly-doped n-type collector region
3
. Boron is ion implanted into the lightly-doped n-type collector region
3
at dosage of 2E13 to 3E13 atom/square-cm under acceleration energy of 15-20 KeV. The ion-implantation mask is stripped off. The boron forms a lightly-doped p-type intrinsic base region
8
.
A photo-resist ion-implantation mask (not shown) is formed on the major surface by using the photo-lithographic techniques, and has an opening over a part of the lightly-doped p-type intrinsic base region
8
. Boron fluoride is ion implanted into the part of the lightly-doped p-type intrinsic base region
8
at dosage of 1E15 to 2E15 atom/square-cm under acceleration energy of 30-50 KeV. The photo-resist ion-implantation mask is stripped off, and boron fluoride forms a heavily-doped p-type graft base region
9
. The resultant semiconductor structure is shown in FIG.
1
A.
Silicon oxide is deposited to 100 nanometers thick over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition, and forms a thick silicon oxide layer
10
. Not only the active area assigned to the bipolar transistor but also the active areas assigned to the field effect transistors are covered with the thick silicon oxide layer
10
.
A photo-resist etching mask (not shown) is formed on the thick silicon oxide layer
10
, and has an opening over a part of the lightly-doped p-type intrinsic base region
8
. The thick silicon oxide layer
10
is selectively etched away, and an emitter contact hole
11
is formed in the thick silicon oxide layer
10
.
Subsequently, polysilicon is deposited to 150 nanometers thick over the entire surface of the resultant semiconductor st
Anya Tgwe U.
McGinn & Gibb PLLC
NEC Corporation
Smith Matthew
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