Semiconductor inspection device capable of performing...

Details Semiconductor inspection device capable of performing... Semiconductor inspection device capable of performing...

2002-08-22

2004-11-09

Pert, Evan (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB, C700S121000

Reexamination Certificate

active

06815969

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor inspection device used when a semiconductor device is inspected and in particular, to a semiconductor inspection device including a plurality of inspection circuits, which are different from each other and conducts a plurality of inspections, and an semiconductor inspection method therefor.
DESCRIPTION OF THE RELATED ART
FIG. 9
is an external view showing a conventional semiconductor inspection device.
Referring to
FIG. 9
, a reference numeral
1
denotes a tester for testing a semiconductor device (hereinafter referred to simply as a tester); a reference numeral
2
a prober for inspecting a semiconductor device (hereinafter referred to simply as a prober); a reference numeral
3
a semiconductor inspection circuit (hereinafter referred to as a DUT board). The DUT board
3
builds therein peripheral circuits for outputting the electric characteristics of the semiconductor device
4
to be inspected (that is, a semiconductor device to be undergone inspection; hereinafter referred to as a DUT), and a conversion circuit for converting the electric characteristics into a measurable signal by a tester
1
for inspecting the semiconductor device and the like by a probe
5
. The DUT
4
and the DUT board
3
are electrically connected to each other.
As shown in
FIG. 10
, the DUT board
3
is mounted with a semiconductor inspection circuit unit (hereinafter referred to as simply an inspection circuit unit)
3
a
, on which the probe (probe needle)
5
is provided. Then, when the DUT
4
is inspected the probe needle
5
is put into contact with (connected to) the DUT
4
to electrically connect the DUT
4
to the inspection circuit unit
3
a
. Here, the tester
1
for inspecting the semiconductor device is connected to the inspection circuit
3
a
via an interface cable
6
a.
Next, the operation of the conventional semiconductor inspection device shown in
FIG. 9
will be described. When the DUT
4
is inspected, first, referring to FIG.
10
and
FIG. 11
, an inspection program and the semiconductor inspection circuit unit
3
a
are designed in accordance with what kind of inspection the DUT
4
conducts. Then, the DUT
4
(for example, wafer) is set on the DUT board
3
and a test (inspection) is started. After the inspection is started, a test start signal is sent to the prober
2
from the tester
1
(step ST
1
). When the prober
2
receives the test start signal, the prober
2
starts probing (step ST
2
). When the probing is started, first, the prober
2
controls the DUT board
3
and electrically connects the inspection circuit unit
3
a
to the DUT
4
by the probe
5
. That is, the inspection circuit unit
3
a
is put into contact with the DUT
4
by the probe
5
(step ST
3
). When the inspection circuit unit
3
a
is contacted with the DUT
4
, an inspection program (test program) is executed and the tester
1
sets inspection items (I) from 1 to J (J: an integer not smaller than 2) in accordance with the test program (step ST
4
). That is, the inspection is started after a plurality of inspection items are set (step ST
5
).
First, the tester
1
inspects the DUT
4
when the inspection item is I=1 and judges the inspection result (step ST
6
). If the inspection result is “good”, the process proceeds to the next inspection item (NEXT J: step ST
7
) and judges the inspection result in the same way. When the tester
1
ends inspecting the inspection items from 1 to J in this manner, that is, if the tester
1
judges that the DUT
4
is not bad in terms of all the inspection items from 1 to J, the tester
1
judges the DUT
4
to be a good product and sends a PASS signal to the prober
2
(step ST
8
). Then, the tester
1
ends the inspection and sends an END signal to the prober
2
(step ST
9
). When the prober
2
receives the END signal, the prober
2
controls the DUT board
3
and ends probing (step ST
10
).
Otherwise, if the DUT is judged to be “bad”, for example, it is judged that the DUT is bad in terms of the inspection item j (j: any one of integers from 1 to J), the tester
1
stops the test at a point of time of the inspection item j (when the DUT is judged to be bad) (step ST
11
). Then, the tester
1
sends a FAIL signal to the prober
2
(step ST
12
). This FAIL signal includes the inspection item j at which the DUT is judged to be bad. In response to the FAIL signal, the prober
2
marks the bad DUT
4
to designate a bad chip (step ST
13
), and further performs a map data processing for the bad DUT
4
on the basis of the FAIL signal (step ST
14
). After the tester
1
sends the FAIL signal, the tester
1
performs a bad category classification (binning) for the bad DUT
4
(step ST
15
) in accordance with how many inspection items j are and ends the inspection. As described above, the tester
1
sends the END signal to the prober
2
and the prober
2
ends probing.
The tests are repeatedly performed for the respective DUTs in the manner described above. In this manner, in the semiconductor inspection device shown in
FIG. 9
, the tester
1
and the prober
2
inspect and judge the DUTs in accordance with the inspection items, and the tester
1
stores the judgment results in the built-in storage circuit, and if the DUT is judged to be bad, the prober
2
marks the bad DUT to discriminate the bad chip.
Alternatively, as shown in
FIG. 12
, the DUT board
3
may be mounted with a plurality of inspection circuits. In
FIG. 12
, the first inspection circuit unit
3
b
and the second inspection circuit unit
3
c
are mounted on the DUT board
3
. The first and the second inspection circuit units
3
b
and
3
c
are provided with the probes
5
a
and
5
b
, respectively, and the DUT
4
a
and the DUT
4
b
are mounted on the first and the second inspection circuit units
3
b
and
3
c
, respectively. The DUTs
4
a
and
4
b
are put into contact with the probes
5
a
and
5
b
, thereby electrically connecting them to the inspection circuit units
3
a
and
3
b
. The tester is connected to the first and the second inspection circuits
3
b
and
3
c
via interface cables
6
b
and
6
c
. The tester shown in
FIG. 12
can test a plurality of DUTs at the same time and is referred to as a multiple tests related tester (indicated by a reference numeral
1
a
in FIG.
12
). The first and the second inspection circuit units
3
b
and
3
c
, which have the same circuit configuration and are connected to pins of the tester
1
a
and are different from each other.
The tests (inspections) of the DUTs
4
a
and
4
b
when the above multiple tests related tester
1
a
will be described with reference to FIG.
13
.
As described in
FIG. 11
, after the DUTs
4
a
and
4
b
are set on the DUT board
3
the test (inspection) is started. After the inspection is started, the tester
1
a
sends a test start signal to the prober
2
(step ST
11
). When the prober
2
receives the test start signal, the prober
2
starts probing (step ST
12
). When the prober
2
starts probing, first, the prober
2
controls the DUT board
3
to electrically connect the first and the second inspection circuit units
3
b
and
3
c
to the DUTs
4
a
and
4
b
by the probes
5
a
and
5
, respectively. That is, the first and the second inspection circuit units
3
b
and
3
c
are put into electrical contact with the DUTs
4
a
and
4
b
by the probes
5
a
and
5
, respectively (step ST
13
). When the first and second inspection circuit units
3
b
and
3
c
are electrically contacted with the DUTs
4
a
and
4
b
, an inspection program (test program) is executed and in accordance with the test program, the tester
1
a
sets the inspection items (I) from 1 to J, that is, sets a plurality of inspection items (step ST
14
) and starts the inspection (step ST
15
).
First, the tester
1
a
inspects the DUTs
4
a
and
4
b
in terms of the inspection item I=1 at the same time and judges the inspection results (steps ST
16
and ST
17
). If the judgment reveals the DUT
4
a
to be “good”, the process proceeds to the nex

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