Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-04-26
2002-03-26
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
C716S030000
Reexamination Certificate
active
06362013
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor inspection apparatus and a method of specifying attributes of dies on a wafer with such a semiconductor inspection apparatus.
2. Description of the Related Art
In the process of fabricating semiconductor circuit devices, it is customary to electrically test and evaluate a wafer before the wafer is cut into chips. In a parametric test using TEGs (Test Element Groups), one or more dies in a central area of the wafer where the probability of occurrence of defective dies is small are tested. If the tested die or dies in the central area of the wafer have no problem, then in peripheral areas of the wafer where probability of occurrence of defective dies is higher more or all dies are tested.
One example of a semiconductor parametric tester for use in such a test will be described below with reference to
FIG. 7
of the accompanying drawings. As shown in
FIG. 7
, a semiconductor parametric test system
1
comprises a tester
3
for supplying an electric signal to a wafer
2
being measured and for measuring an electric signal from the wafer
2
, a prober
5
for removing a wafer
2
to be measured from a wafer lot
4
and bringing probes into contact with a certain die on the removed wafer
2
, a computer
6
A for controlling the tester
3
and the wafer prober
5
to process measured data, and a group of measuring programs
6
B for operating the computer
6
A. The measuring program group
6
B has a test plan
7
comprising an information file concerning the wafer
2
and devices fabricated thereon, a measuring algorithm library
8
comprising a file defining a measuring algorithm, a core program
9
for such functions as initializing various parts and loading and executing the test plan
7
and the measuring algorithm library
8
, and a limit file
10
. The measuring program group
6
B also includes a user interface program
9
a
for receiving information from and giving information to the operator via a display unit and a keyboard. Each of the test plan
7
, the measuring algorithm library
8
, and the limit file
10
has a fill-in-the-box builder for the user to generate a file easily.
The test plan
7
includes a wafer specification
7
a
for defining the names, positions, and other attributes of dies on a wafer, a die specification
7
b
for defining the names and positions of modules on dies, a prober specification
7
c
for defining connections between device pads on the prober card in the wafer prober
5
and pins of a switching matrix, and a test specification
7
d
for defining a measuring algorithm for use in a device test.
For establishing the test plan
7
, data concerning an entire wafer such as of the index and dimensions of the wafer and attributes of individual dies on the wafer are specified in the step of the wafer specification
7
a
. Dies refer to a plurality of chip regions produced on a semiconductor wafer. In many cases, dies in a peripheral area of a wafer are not used in the actual fabrication of semiconductor circuit devices, and are specified as marker dies for identifying other dies. Depending on the dimensions of the wafer and dies, such marker dies need to be manually specified. In addition, various tests, e.g., a DC conduction test, need to be specified as one of the attributes of predetermined dies. If a certain test fails, then a preliminary die may be required to be designated as a die to be tested next.
A die normally comprises several modules that are put together into a single set. The configuration of modules within individual dies is specified as the die specification
7
b
. The prober specification
7
c
is specified depending on the type of a probe card used for dies. A test to be conducted finally is specified as a measuring algorithm which is referred to as the test specification
7
d
. When the above data are specified to complete the test plan
7
, the test plan
7
is loaded by the core program
9
, and an actual test is carried out.
The parametric tester conducts a test of electric characteristics on a plurality of chip regions (dies) on a semiconductor wafer according to a die sorting test process. In this test, the probe of the wafer prober is held in contact with the dies. In recent years, as the yield of dies increases, not all the dies are tested, but only selected dies are tested, and if the tested dies are not defective, then the wafer is sent to a next fabrication process for increased productivity. The dies to be tested are selected in advance. Since defective dies tend to occur in the peripheral area of a wafer, many dies to be tested are selected in the peripheral area of the wafer. Therefore, it is not customary to place dies to be tested at equal intervals over the entire wafer.
When selecting dies on a wafer for a test, it has heretofore been difficult to select those dies particularly in the peripheral area of the wafer because of lack of suitable markers especially if the number of dies is large. It has been the conventional practice to display coordinate values at given distances or plot colors or patterns instead of graduations for assisting in selecting dies to be tested. Since such plotted assistive marks are mechanically applied, they fail to provide a useful relationship between different die layouts on individual wafers at the time when various types of semiconductor devices are manufactured on one production line, and hence are not effective enough as markers for complex die layouts particularly in the peripheral area of wafers.
Positional information relative to markers used for specifying dies to be tested has heretofore been managed as data of attributes different from data directly required for tests, indicative of whether dies are to be selected or not. The positional information thus managed as separate data is separate from the data required for the test, resulting in the need for data for associating these data with each other, which make the data management complex. For editing the data of the different attributes, because the data are managed separately, it is necessary to clearly indicate data to be edited, display the data on a display screen, and then edit the data in question, and to edit the data using tools that are different for individual data attributes. Accordingly, it has been tedious and time-consuming to edit data of different attributes. For example, a mode for selecting a die that serves as a marker and a mode for specifying a die to be tested may be different from each other, and these modes have to be switched for selecting and specifying dies.
Different data are displayed in an overlapping fashion on the same display screen. For example, 1) a die to be tested actually, 2) a die that serves as a marker in an editing process, 3) an initial position where an electric connection is to be made to a die by a wafer prober, and 4) a cursor on a die being presently edited, are displayed in an overlapping manner. However, data are prepared for each purpose of attributes and they are handled in a multiple mode only when displayed, and need to be edited separately for different attributes. For example, if a die to be tested is specified after a die that serves as a marker in the editing process is specified, then these specified dies are simultaneously displayed, but it is necessary to switch between modes in order to specify dies of different types.
The need for switching between modes makes it difficult for an operator who is not skilled enough to recognize how the testing process is in progress. The failure to recognize the proper testing sequence tends to cause errors.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a unified management of data required for a test and information needed for specifying a die to be tested, so that data of different kinds can be handled together.
The present invention provides a means for managing multi-valued data of plural attributes for a die on a wafer in a unified manner, and displaying the managed data as graphical
Agilent Technologie,s Inc.
Bowers Charles
Smoot Stephen W.
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